• Proceedings of the IEEK Conference
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.353-356
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• 1999

A 3.3V PLL(Phase Locked loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage to frequency linearity of VCO(Voltage controlled oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30MHz~1㎓ with a good linearity. The DC-DC voltage up/down converter is utilized to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6${\mu}{\textrm}{m}$ n-well CMOS process. The simulation results show a locking time of 2.6$\mu$sec at 1Hz, Lock in range of 100MHz~1㎓, and a power dissipation of 112㎽.

• Journal of the Semiconductor & Display Technology
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• 제14권2호
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• pp.35-40
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• 2015

This paper presents the sensorless position control of the Permanent Magnet Synchronous Motor (PMSM) using stator flux estimation and Phase Lock Loop (PLL). The field current and the torque current are required in order to perform the vector control of the PMSM. At this time, it is necessary for the torque to know the exact position of the magnetic flux generated by the permanent magnet, because the torque must be applied torque current in the direction orthogonal to the permanent magnet. In general the speed of the PMSM is controlled by using a magnetic position sensor. However, this paper, we estimates the stator flux by using the PLL method without the magnetic position sensor. This method is simple and easy, in addition it has the advantage of a stabile estimation of the rotor. Finally the proposed algorithm was confirmed by experimental results and showed the good performance.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.313-317
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• 2003

In this paper, ultra-wideband frequency synthesizer which operates at S-band ($2{\sim}4GHz$) is designed. Designed frequency synthesizer shows the frequency range of $2.2{\sim}4.0GHz$ and output power of $-2{\sim}3dBm$. Phase noise characteristics are measured below -92.0dBc/hz at 100kHz offset frequency in entire sweep range and lock time is measured below 3.55ms. Spurious level is below -62.33dBc at comparison frequency of 1MHz.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.963-964
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• 2006

By combining a digital DLL and an analog DLL in 2-stage, an improved DLL is implemented in this paper. The proposed DLL is composed of a RDLL (Register Controlled DLL) and a conventional analog DLL. The phase comparator used in the DLL is built with sense-amp based D flip-flops for high speed operation. The proposed DLL circuits have been designed, simulated in 0.18um, 1.8V TSMC CMOS library. The implemented DLL have demonstrated the fast lock-on time of 1us and low jitter of 72ps.

• Proceedings of the KIEE Conference
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 B
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• pp.582-584
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• 1998

IEEE1394 is an international standard that will integrate entertainment, communication, and computing electronics into consumer multimedia. IEEE1394 is a hardware and software for transporting data at 100,200, or 400Mbps. There are efforts to create speed improvements to 800 and muti-Gigabit speed s. An 980Mhz frequency synthesizer is proposed for high speed transport and designed by a 0.35um CMOS process.

• Journal of the Institute of Electronics and Information Engineers
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• 제50권2호
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• pp.122-133
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• 2013

An arbiter-based simple phase decision circuit (PDC) optimized for high-resolution phase-to-digital converter made up of an analog phase-frequency detector and a time-to-digital converter for all-digital phase-locked loops is proposed. It can distinguish very small phase difference between two pulses even though it consumes lower power and has smaller input-to-output delay than the previously reported PDC. Proposed PDC is realized using 130-nm CMOS process and demonstrated by transistor-level simulations. A 5-bit P2D having no offset nor deadzone using the PDC is also demonstrated. A harmonic-lock-free and small-phase-offset delay-locked loop for fixing the P2D resolution regardless of PVT variations is also proposed and demonstrated.

• The Journal of the Acoustical Society of Korea
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• 제29권4호
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• pp.229-236
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• 2010

Phase coherent modulation techniques in underwater acoustic channel can improve bandwidth efficiency and data reliability, but they are made difficult by time-varying intersymbol interference. This paper proposes an adaptive equalizer combined with phase estimator which compensates distortions caused by time-varying multipath and phase variation. The experiment in the East sea demonstrates phase coherent signals are distorted by time-varying multipath propagation and the proposed scheme equalizes them. Bit error rate of BPSK and QPSK are 0.0078 and 0.0376 at 300 meter horizontal distance and 0.0146 and 0.0293 at 1000 meter respectively.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• 제20권8호
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• pp.88-95
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• 2006

This paper proposes an analog type Active Power Filter that adapts to the frequency change of a distributed power supply system. The proposed system removes the harmonic currents in the source power by injecting a compensation current that has the same frequency, 180 degree out of phase with the harmonic currents generated by the load. The detection of the harmonics in the source power for creating the compensating current is realized by a PLL(Phase Lock Loop) and a VCGIC(Voltage Controlled Generalized Impedance Converter). The operation of the proposed system is verified by simulation and experiment.

• Journal of Positioning, Navigation, and Timing
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• 제3권3호
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• pp.107-116
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• 2014

When an incoming Global Positioning System (GPS) signal is acquired, pull-in search performs a finer search of the Doppler frequency of the incoming signal so that phase lock loop can be quickly stabilized and the receiver can produce an accurate pseudo-range measurement. However, increasing the accuracy of the Doppler frequency estimation often involves a higher computational cost for weaker GPS signals, which delays the position fix. In this paper, we show that the Doppler frequency detectable by a long coherent auto-correlation can be accurately estimated using a complex-weighted sum of consecutive short coherent auto-correlation outputs with a different Doppler frequency hypothesis, and by exploiting this we propose a noise resistant, low-cost and highly accurate Doppler frequency and phase estimation technique based on a reverse directional application of the finite rate of innovation (FRI) technique. We provide a performance and computational complexity analysis to show the feasibility of the proposed technique and compare the performance to conventional techniques using numerous Monte Carlo simulations.

• The Transactions of The Korean Institute of Electrical Engineers
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• 제60권2호
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• pp.451-454
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• 2011

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.