• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.3 no.2 s.5
• /
• pp.69-74
• /
• 2004

In this work, A PLDRO (Phase Locked Dielectric Resonator Oscillator) which can be used for the wireless communication systems fur MMC(Microwave Micro Cell) and ITS wireless communication system is designed. A different approach to the PLDRO structure is applied for phase locking by dual phase lock loop structure. The proposed dual loop PLDRO generates the output power of 0 dBm at 18.7 GHz and has the characteristics of a phase noise of -80 dBc/Hz at 1kHz, -83 dBc/Hz at 10 kHz offset frequency from carrier frequency

• Transactions on Electrical and Electronic Materials
• /
• v.18 no.4
• /
• pp.185-189
• /
• 2017

This paper proposes a low power frequency divider for an integrated CMOS phase-locked loop (PLL). An injection-locked frequency divider (ILFD) was designed, along with a current-mode logic (CML) frequency divider in order to obtain a broadband and high-frequency operation. A ring oscillator was designed to operate at 1.2 GHz, and the ILFD was used to divide the frequency of its input signal by two. The structure of the ILFD is similar to that of the ring oscillator in order to ensure the frequency alignment between the oscillator and the ILFD. The CML frequency divider was used as the second stage of the divider. The proposed frequency divider was applied in a conventional PLL design, using a 0.18 ${\mu}m$ CMOS process. Simulation shows that the proposed divide-by-two ILFD and the divide-by-eight CML frequency dividers operated as expected for an input frequency of 1.2 GHz, with a power consumption of 30 mW.

• Journal of Advanced Navigation Technology
• /
• v.3 no.1
• /
• pp.1-12
• /
• 1999

For the phase measurement of radar signal in the coherent-on-receiver system, the COHO(Coherent Oscillator) generates the signal which locks to the phase of the transmit pulse. In this paper, COHO unit is developed to generate 60 MHz phase-locked signal. ILO(Injection Locking Oscilator) locks to the sample of the transmit pulse. Gate circuit, ILO, buffer amplifier, and pulse generator are designed and implemented.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.25 no.6
• /
• pp.671-678
• /
• 2014

This paper presents a Ka-band FMCW sensor that has high linearity by improving a nonlinear behavior of the voltage controlled oscillator. Due to the nonlinear characteristics of the voltage controlled oscillator for the conventional method, the drift of beat frequency can cause inaccuracy and errors to the extracted results. A Ka-band FMCW signal with fast transition time could be generated by using both direct digital synthesizer and phase locked loop in this research. The implemented FMCW sensor showed very high accuracy in beat frequency through the test.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.5
• /
• pp.522-527
• /
• 2011

In this work, a 54 GHz divide-by-3 injection-locked frequency divider(ILFD) based on ring oscillator has been developed in a 0.13-${\mu}M$ Si RFCMOS technology for phase-locked loop(PLL) application. The free-running frequency is 18.92~19.31 GHz with tuning range of 0~1.8 V, consuming 70 mW with a 1.8 V supply voltage. At 0 dBm input power, the locking range is 1.02 GHz(54.82~55.84 GHz) and, with varactor tuning of 0~1.8 V, the total operating range is 2.4 GHz(54.82~57.17 GHz). The fabricated circuit size is 0.42 mm${\times}$0.6 mm including probing pads and 0.099 mm${\times}$0.056 mm for core area.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.12C
• /
• pp.268-272
• /
• 2001

In this thesis, PLVCO(Phase Locked Voltage Controlled Oscillator) using 24.42 GHz voltage controlled hair-pin resonator oscillator, Sequency divider, buffer amplifier, -10 dB directional coupler and phase detector is designed and fabricated for B-WLL. The PLVCO shows the oscillator output power of 16.5 dBm at 24.42 GHz, and phase noise of -76.3 dBc/Hz at 1001:Hz offset, -72.8dBc/Hz at 10 kHz offset from fundamental frequency.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.19 no.3
• /
• pp.379-386
• /
• 2016

In this paper, phase noise analysis result for 2.4 GHz PLL(phase locked loop) using SPD(sample phase detector) is proposed. It can be used for high performance frequency synthesizer's LO(local oscillator) to extend output frequency range or for LO of offset PLL to reduce a division rate or for clock signal of DDS(direct digital synthesizer). Before manufacturing, theoretical estimation of PLL's phase noise performance should be performed. In order to calculate phase noise of PLL using SPD, Leeson model is used for modeling phase noise of VCO(voltage controlled oscillator) and OCXO(ovened crystal oscillator). After theoretically analyzing phase noise of PLL, optimized loop filter bandwidth was determined. And then, phase noise of designed loop filter was calculated to find suitable OP-Amp. Also, the calculated result of phase noise was compared with the measured one. The measured phase noise of PLL was -130 dBc/Hz @ 10 kHz.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.2A
• /
• pp.194-200
• /
• 2006

A 26.4 GHz phase locked oscillator(PLO) for communication satellite transponder is developed. The PLO consists of fundamental frequency generation module(FFGM) and frequency multiplication part(FMP). The signal of 26.4 GHz is generated through frequency tripling process of 8.8 GHz fundamental frequency. Phase locking technique using sampling phase detector(SPD) is adopted to design the FFGM. The MMIC tripler and amplifier are also designed for the reduction of the size and mass of FMP. The phase noise characteristics are exhibited as -96 dBc/Hz at 10 tHz offset frequency and -105 dBc/Hz at 100 kHz offset frequency, respectively, with the output power over 11 dBm. All performance parameters are complied with the design requirements.

• Journal of Power Electronics
• /
• v.18 no.5
• /
• pp.1523-1535
• /
• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• Journal of IKEEE
• /
• v.15 no.1
• /
• pp.29-36
• /
• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC is employed to overcome the problems of dithering scheme. A 2.4GHz LC-based DCO has been designed in a $0.13{\mu}m$ CMOS process with an enhanced frequency resolution for wireless local area network applications. It has a frequency tuning range of 900MHz and a resolution of 58.8Hz. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The designed DCO exhibits a phase noise of -123.8dBc/Hz at 1MHz frequency offset. The DCO core consumes 4.2mA from 1.2V supply.