• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.309-314
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• 2006

In general DGPS system, the correction message is transferred to users by wireless modem. To cover wide area, many DGPS station should be needed. And DGPS users must have a wireless modem that is not necessary in standalone GPS. But SBAS users don't need a wireless modem to receive DGPS corrections because SBAS correction message is transmitted from the GEO satellite by L1 frequency band. SBAS signal is generated in the GUS(Geo Uplink Subsystem) and uplink to the GEO satellite. This uplink transmission process causes two problems that are not existed in GPS. The one is a time delay in the uplink signal. The other is an ionospheric problem on uplink signal, code delay and carrier phase advance. These two problems cause ranging error to user. Another critical ranging error factor is clock synchronization. SBAS reference clock must be synchronized with GPS clock for an accurate ranging service. The time delay can be removed by close loop control. We propose uplink ionospheric error correcting algorithm for C/A code and carrier. As a result, the ranging accuracy increased high. To synchronize SBAS reference clock with GPS clock, I reviewed synchronization algorithm. And I modified it because the algorithm didn't consider doppler that caused by satellites' dynamics. SBAS reference clock synchronized with GPS clock in high accuracy by modified algorithm. We think that this paper will contribute to basic research for constructing satellite based DGPS system.

• Journal of Positioning, Navigation, and Timing
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• v.10 no.4
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• pp.379-385
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• 2021

In order to synchronize a remote system time to the reference time like Coordinated Universal Time (UTC), it is required to compare the time difference between the two clocks. GNSS Precise Point Positioning (PPP) is one of the most general geodetic positioning methods and can be used for time and frequency transfer applications which require more precise time comparison performance than GNSS code. However, the PPP technique has a main drawback of day-boundary discontinuity which comes from the PPP model that the code measurements are applied to resolve the floating carrier-phase ambiguities. The Integer PPP (IPPP) technique is one of the methods which has been studied to compensate the day-boundary discontinuities exited in the conventional PPP. In this paper, we investigate the time and frequency capabilities of PPP and IPPP by using the measurement data obtained from two time transfer receivers which are closely located and using common reference 1 Pulse Per Second (PPS) and RF signals. From the experiment, it is investigated that the IPPP method can effectively compensate the day-boundary discontinuities without producing frequency offset. However, the PPP method can generating frequency offset which can severely degrade the time comparison performance with long-term period data.

• The Journal of the Acoustical Society of Korea
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• v.24 no.1
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• pp.11-20
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• 2005

In this paper, we deal with the research about a S/PDIF (Sony Philips Digital Interface) receiver which can operate without PLL (Phase Locked Loop) circuits. Although a S/PDIF receiver is used in most audio devices and audio processors in these days. yet there are only few domestic researches about S/PDIF. Currently used commercial DACs (Digital-to-Analog Converters) which can decode S/PDIF signals, have a PLL circuit inside them. The PLL makes it possible to extract clock information from S/PDIF digital signal and to synchronize a clock signal with input signals. But the PLL circuit makes many diffculties in designing the SOC (System On Chips) of VLSIs (Vew Large Scale Integrated Ciruits) because it is an "analog circuit". We proposed a S/PDIF receiver which doesn't have PLL circuits and only has Pure digital circuits. The key idea of the proposed S/PDIF receiver. is to use the ratio between a 16 MHz basic input clock and S/PDIF signals. After having decoded hundreds thousands S/PDIF inputs, it went to prove that a S/PDIF receiver can be designed with pure digital circuits and without any analog circuits such as PLL circuits. We have confidence that the proposed S/PDIF receiver can be used as an IP (Intellectual Property) for the SOC design of the digital circuits.

• Journal of Korean Society for Quality Management
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• v.41 no.4
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• pp.725-735
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• 2013

Purpose: The purpose of this study is to propose an Integrated Safety Evaluation Process (ISEP) that can enhances the safety aspect of the safety-critical system. This process utilizes the advantages of the iterative Systems Engineering process combined with the safety assessment process that is commonly and well defined in many standards and/or guidelines for railway, aerospace, and other safety-critical systems. Methods: The proposed process model is based on the predefined system lifecycle, in each phase of which the appropriate safety assessment activities and the safety data are identified. The interfaces between Systems Engineering process and the safety assessment process are identified before the two processes are integrated. For the integration, the elements at lower level of Systems Engineering process are combined with the relevant elements of safety assessment process. This combined process model is represented as Enhanced Functional Flow Block Diagram (EFFBD) by using CORE(R) that is commercial modelling tool. Results: The proposed model is applied to the lifecycle and management process of the United States aircraft system. The US aircraft systems engineering process are composed of twelve key elements, among which the requirements management, functional analysis, and Synthesis processes are considered for examplenary application of the proposed process. To synchronize the Systems Engineering process and the safety assessment process, the Systems Engineering milestones are utilized, where the US aircraft system has thirteen milestones. Taking into account of the nine steps in the maturity level, the integrated process models are proposed in some phases of lifecycle. The flows of processes are simulated using CORE(R), confirming the flows are timelined without any conflict between the Systems Engineering process and the safety assessment process. Conclusion: ISEP allows the timeline analysis for identifying activity and data flows. Also, the use of CORE(R) is shown to be effective in the management and change of process data, which helps for the ISEP to apply for the development of safety critical system. In this study, only the first few phases of lifecyle are considered, however, the implementation through operation phases can be revised by combining the elements of safety activities regarding those phases.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.3
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• pp.123-128
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• 2021

For accurate speed and current control in industrial applications, SRM (Switched Reluctance Motor) is very important to synchronize the stator phase excitation and rotor position in the drive due to its nature. In general, position sensors such as encoder and resolver are used to generate rotational force by exciting the stator winding according to the rotor position and to control the motor by using speed and position information. However, for these sensors, 1) the cost of the sensors is quite large in terms of price, so the proportion of the motor system to the total system cost is high. 2) In terms of mechanical, position sensors such as encoders and resolvers are attached to the stator to increase the size and weight. In conclusion, in order to drive the SRM, control based on the rotor position information should be basically performed, and it is important to design the SRM driving system according to the environment in consideration of the application field. Therefore, in this paper, we intend to study the driving and control characteristics of SRM through variable switching duty control by designing a low-cost analog driving device, deviating from the general control system using the conventional encoder and resolver.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.45-53
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• 2007

To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.