• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.71-79
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• 1990

An analog phase shifter is designed at the operating frequency 10GHz that is coupled with a hybrid ring and the network connecting an inductor series with a varactor to extend a continuous chage in the phase of the reflected output wave to be produced from a variation in the terminated varactor reactance as a variation in the reverse bias voltage. It is manufactured in a microstripline in consideration of an effect of the dispersion characteristics and discontinuities. As a resuls of an experiment, a change in the phase is achieved over 180 degree from $52.34^{\circ}$ degrees to $235.01^{\circ}$degrees, the transmission loss is -3.6~-14.3dB, and the return loss is -16~-8dB(1.37

• The Transactions of the Korean Institute of Electrical Engineers
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• v.44 no.8
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• pp.1068-1074
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• 1995

Effect of (Zn$_{1}$3/Nb$_{2}$3/) $O_{2}$ addition on the phase changes and microwave dielectric properties of BaTi $O_{3}$-3Ti $O_{2}$ ceramics were investigated. Addition of (Zn$_{1}$3/Nb$_{2}$3/) $O_{2}$ to BaTi $O_{3}$-3Ti $O_{2}$ resulted in the formation of Ba $Ti_{4}$$O_{9}$, $Ba_{2}$ $Ti_{9}$ $O_{20}$, Ba(Zn$_{1}$3/Nb$_{2}$3/) $O_{3}$, and Ti $O_{2}$ phases. Ba $Ti_{4}$$O_{9}$ phase was gradually transformed to $Ba_{2}$ $Ti_{9}$ $O_{20}$. This was identified by XRD and microstructure. As the Ba $Ti_{4}$$O_{9}$ phase transformed to $Ba_{2}$ $Ti_{9}$ $O_{20}$ phase, the dielectric constant increased to 37.5. Q*f$_{o}$ value was 40000 at x=0.04, and the temperature coefficient of resonant frequency was +10ppm/.deg. C.C.. C.C.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.401-417
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• 1994

In this paper, a new testable design technique for domino CMOS circuits is proposed to detect stuck-at(s-at), stuck-open(s-op) and stuck-on(s-on) faults in the circuits by observing logic test reponses. The proposed technique adds one pMOS transistor per domino CMOS gate for s-op and s-on faults testing of nMOS transistors and one nMOS transistors and one nMOS transistor per domino gate or multilevel circuit to detect s-on faults in pMOS transistors of inverters in the circuit. The extra transistors enable the proposed testable circuit to operate like a pseudo static nMOS circuit while testing nMOS transistors in domino CMOS circuits. Therefore, the two=phase operation of a precharge phase and a evaluation phase is not needed to keep the domino CMOS circuit from malfunctionong due to circuit delays in the test mode, which reduces the testing time and the complexity of test generation. Most faults of th transistors in the proposed testable domino CMOS circuit can be detected by single test patterns. The use of single test patterns makes the testing of the proposed testable domino CMOS circuit free from path delays, timing skews, chage sharing and glitches. In the proposed design, the testing of the faults which, require test sequences also becomes free from test invalidation. The conventional automatic test pattern generators(ATPG) can be used for generating test patterns to detect faults in the circuits.