• 한국컴퓨터정보학회논문지
• /
• 제16권10호
• /
• pp.11-21
• /
• 2011

본 논문에서는 멀티미디어에 내재한 무수한 데이터를 효율적으로 처리할 수 있는 SIMD(Single Instruction Multiple Data) 기반 병렬 프로세서를 소개한다. 또한, 인텔사의 대표적인 멀티미디어 전용 명령어인 MMX (MultiMedia eXtension)타입 명령어를 병렬 프로세서에 구현하여 성능을 평가하고 결과를 분석한다. 16개의 32-비트 프로세서로 구성된 병렬프로세서를 이용하여 1280x1024픽셀 이미지의 JPEG 압축 애플리케이션을 구현하고 모의 실험한 결과, 동일한 병렬프로세서 기반에서 MMX타입 명령어는 베이스라인 명령어보다 약 50%의 성능 향상을 보였다. 또한, MMX타입 명령어는 베이스라인 명령어보다 에너지 효율에서 100%, 시스템 면적 효율에서 51%의 향상을 보였다. 이러한 결과는 MMX를 포함한 멀티미디어 전용 명령어들이 현재 널리 사용되고 있는 매니코어 GPU(Graphics Processing Unit) 및 다양한 형태의 병렬프로세서에서도 잠재 가능성이 있음을 보여준다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(3)
• /
• pp.29-32
• /
• 2001

In this paper, we applied the high-performance PGAP(Parallel Genetic Algorithm Processor) to recognizing rotated pattern. In order to perform this research efficiently, we used Multi-PGAP system consisted of four PGAP. In addition, we used mental rotation based on the rotated pattern recognition mechanism of human to reduce the number of operation. Also, we experimented with distinguishing specific pattern from similar coin patterns and determine rotated angle between patterns. The result showed that the development of future artificial recognition system is feasible by employing high performance PGAPS.

• 한국경영과학회:학술대회논문집
• /
• 대한산업공학회/한국경영과학회 1991년도 춘계공동학술대회 발표논문 및 초록집; 전북대학교, 전주; 26-27 Apr. 1991
• /
• pp.6-22
• /
• 1991

This thesis presents a parallel implementation of an iterative method for large scale, sparse linear system and gives result of computational experiments performed on both single transputer and multi transputer parallel computers. To solve linear system, we use conjugate gradient method and develope data storage techinique, data communication scheme. In addition to the explanation of conjugate gradient method, the result of computational experiment is summarized.

• 전자공학회논문지C
• /
• 제34C권11호
• /
• pp.47-55
• /
• 1997

In general, processing flow of the conventional floating-point multiplication consists of either multiplication, addition, normalization, and rounding stage of the conventional floating-point multiplier requries a high speed adder for increment, increasing the overall execution time and occuping a large amount of chip area. A floating-point multiplier performing addition and IEEE rounding in parallel is designed by using the carry select addder used in the addition stage and optimizing the operational flow based on the charcteristics of floating point multiplication operation. A hardware model for the floating point multiplier is proposed and its operational model is algebraically analyzed in this paper. The proposed floating point multiplier does not require and additional execution time nor any high spped adder for rounding operation. Thus, performance improvement and cost-effective design can be achieved by this suggested approach.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2008년도 하계학술대회 논문집
• /
• pp.24-27
• /
• 2008

For high voltage DC-DC converters, the parallel operation of several high voltage source modules is necessary to reduce the material cost. In the conventional parallel operation with HDC module control unit, it is difficult to repair the HDC system for the failure of control unit. To overcome these problems, new parallel operating algorithm for high voltage DC-DC converter is presented. The proposed algorithm has no main control unit and each module can be selected as the master according to the operating conditions. Therefore, one of modules can be replaced as the master immediately when the previous master module is failed. In addition, the extension of extra modules can be simple.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제13권5호
• /
• pp.465-472
• /
• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• 제어로봇시스템학회논문지
• /
• 제12권10호
• /
• pp.1035-1043
• /
• 2006

In this study, a translational 3-DOF parallel mechanism formed by constraining the Stewart Platform Mechanism is investigated. The translational 3-DOF parallel mechanism has three struts(3-UPS type serial subchains) and in addition, has a PPP type serial subchain in the middle of the mechanism. Firstly, the closed-form forward and reverse position solutions are derived for this mechanism. And analysis on kinematic characteristics using isotropic index of the Jacobian is conducted to examine effects of design parameters for the mechanism. Lastly, a prototype mechanism is implemented and the kinematic performance of the translational 3-DOF parallel mechanism was verified through experimental work.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 ITC-CSCC -1
• /
• pp.245-248
• /
• 2000

This paper proposes a cooperative parallel tabu search which incorporates with the historical information exchange among processors in addition to its own searching of each processor. We investigate the influence of our proposed cooperative parallel tabu search by comparison with a serial tabu search. We also propose two extensions of the cooperative parallel tabu search which are the cooperative construction of tabu memory and the selection of cooperative partner. Through computational experiment, we observe the improvement of solutions by our proposed method.

• 설비공학논문집
• /
• 제21권2호
• /
• pp.87-93
• /
• 2009

Slim telecommunication cabinet cooler, equipped with parallel flow heat exchangers and operating with R-22, is developed. The performance is compared with imported one, equipped with fin-tube heat exchangers and operating with R-134a. Test results show that the newly-developed cooler increases the cooling capacity by 6% and EER by 33%. The refrigerant charge for the developed cooler is 500g compared with 1250g for the imported one. The adoption of parallel flow heat exchanger appears to have reduced the refrigerant charge. In addition, it is shown that the reduced air flow rates through parallel heat exchangers as compared with those through fin-tube heat exchangers are beneficial to the reduction of the equipment noise.

• 전기학회논문지
• /
• 제58권9호
• /
• pp.1706-1713
• /
• 2009

In this paper, a parallel operation algorithm for high power PEMFC generation systems is proposed. According to increasing the capacity of fuel cell systems with several fuel cell stacks, the different dynamic characteristics of each fuel cell stack effect on imbalance of load sharing and current distribution, so that a robust parallel operation algorithm is desired. Therefore, a power-sharing technique is developed and explained in order to design an optimal distributed PEMFC generation system. In addition, an optimal controller design procedure for the proposed parallel operation algorithm is introduced, along with informative simulations and experimental results.