• 제목/요약/키워드: Parallel-Addition

Search Result 1,052, Processing Time 0.025 seconds

A Study on the Timetable Using Parallel Population Evolution Programs (병렬 모집단 진화프로그램을 이용한 강의시간표 작성에 관한 연구)

  • 박유석;김병재
    • Journal of Korean Society of Industrial and Systems Engineering
    • /
    • v.22 no.52
    • /
    • pp.275-284
    • /
    • 1999
  • The TTP(TimeTabling Problem) for a university which should be made every term is very difficult problem to schedule because each component must satisfy all fixed constraints. This TTP, therefore, is solved by several heuristic methods. In this paper, applying PPEP(Parallel Population Evolution Programs) for the TTP, we try to find the approximated optimal solution by maintaining independence of each subpopulation and by searching the wide feasible solution. In addition, we present the problem to be appeared when used PMX(Partially mapped crossover)operator for the long chromosomes and then propose GBX (Gene_Based crossover)operator which can complement it. Finally, experimental results are presented comparing EP(Evolution Programs) and PPEP, then GBX which has the random genes and the selected genes on a real TTP.

  • PDF

On-Chip Bus Serialization Method for Low-Power Communications

  • Lee, Jae-Sung
    • ETRI Journal
    • /
    • v.32 no.4
    • /
    • pp.540-547
    • /
    • 2010
  • One of the critical issues in on-chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low-power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word-to-word and bit-by-bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG-4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost-effective when implemented as a hardware circuit since its algorithm is very simple.

A Study on VLSI-Oriented 2-D Systolic Array Processor Design for APP (Algebraic Path Problem) (VLSI 지향적인 APP용 2-D SYSTOLIC ARRAY PROCESSOR 설계에 관한 연구)

  • 이현수;방정희
    • Journal of the Korean Institute of Telematics and Electronics B
    • /
    • v.30B no.7
    • /
    • pp.1-13
    • /
    • 1993
  • In this paper, the problems of the conventional special-purpose array processor such as the deficiency of flexibility have been investigated. Then, a new modified methodology has been suggested and applied to obtain the common solution of the three typical App algorithms like SP(Shortest Path), TC(Transitive Closure), and MST(Minimun Spanning Tree) among the various APP algorithms using the similar method to obtain the solution. In the newly proposed APP parallel algorithm, real-time Processing is possible, without the structure enhancement and the functional restriction. In addition, we design 2-demensional bit-parallel low-triangular systolic array processor and the 1-PE in detail. For its evaluation, we consider its computational complexity according to bit-processing method and describe relationship of total chip size and execution time. Therefore, the proposed processor obtains, on which a large data inputs in real-time, 3n-4 execution time which is optimal o(n) time complexity, o(n$^{2}$) space complexity which is the number of total gate and pipeline period rate is one.

  • PDF

Implementation of Particle Swarm Optimization Method Using CUDA (CUDA를 이용한 Particle Swarm Optimization 구현)

  • Kim, Jo-Hwan;Kim, Eun-Su;Kim, Jong-Wook
    • The Transactions of The Korean Institute of Electrical Engineers
    • /
    • v.58 no.5
    • /
    • pp.1019-1024
    • /
    • 2009
  • In this paper, particle swarm optimization(PSO) is newly implemented by CUDA(Compute Unified Device Architecture) and is applied to function optimization with several benchmark functions. CUDA is not CPU but GPU(Graphic Processing Unit) that resolves complex computing problems using parallel processing capacities. In addition, CUDA helps one to develop GPU softwares conveniently. Compared with the optimization result of PSO executed on a general CPU, CUDA saves about 38% of PSO running time as average, which implies that CUDA is a promising frame for real-time optimization and control.

Document Summarization using Semantic Feature and Hadoop (하둡과 의미특징을 이용한 문서요약)

  • Kim, Chul-Won
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.18 no.9
    • /
    • pp.2155-2160
    • /
    • 2014
  • In this paper, we proposes a new document summarization method using the extracted semantic feature which the semantic feature is extracted by distributed parallel processing based Hadoop. The proposed method can well represent the inherent structure of documents using the semantic feature by the non-negative matrix factorization (NMF). In addition, it can summarize the big data document using Hadoop. The experimental results demonstrate that the proposed method can summarize the big data document which a single computer can not summarize those.

Infrastructure of Grid-based Distributed Remotely Sensed Images Processing Environment and its Parallel Intelligence Algorithms

  • ZHENG, Jiang;LUO, Jian-Cheng;Hu, Cheng;CHEN, Qiu-Xiao
    • Proceedings of the KSRS Conference
    • /
    • 2003.11a
    • /
    • pp.1284-1286
    • /
    • 2003
  • There is a growing demand on remotely sensed and GIS data services in modern society. However, conventional WEB applications based on client/server pattern can not meet the criteria in the future . Grid computing provides a promising resolution for establishing spatial information system toward future applications. Here, a new architecture of the distributed environment for remotely sensed data processing based on the middleware technology was proposed. In addition, in order to utilize the new environment, a problem had to be algorithmically expressed as comprising a set of concurrently executing sub-problems or tasks. Experiment of the algorithm was implemented, and the results show that the new environmental can achieve high speedups for applications compared with conventional implementation.

  • PDF

Load and Mutual Inductance Identification Method for Series-Parallel Compensated IPT Systems

  • Chen, Long;Su, Yu-Gang;Zhao, Yu-Ming;Tang, Chun-Sen;Dai, Xin
    • Journal of Power Electronics
    • /
    • v.17 no.6
    • /
    • pp.1545-1552
    • /
    • 2017
  • Identifying the load and mutual inductance is essential for improving the power transfer capability and power transfer efficiency of Inductive Power Transfer (IPT) systems. In this paper, a steady-state load and mutual inductance identification method focusing on series-parallel compensated IPT systems is proposed. The identification model is established according to the steady-state characteristics of the system. Furthermore, two sets of identification results are obtained, and then they are analyzed in detail to eliminate the untrue one. In addition, the identification method can be achieved without extra circuits so that it does not increase the complexity of the system or the control difficulty. Finally, the feasibility of the proposed method has been verified by simulation and experimental results.

Design and Control of DC/AC Converters in Parallel with Diode Rectifiers for Regenerative Applications

  • Gao, Zhigang;Li, Rui;Lu, Qi
    • Journal of Power Electronics
    • /
    • v.17 no.4
    • /
    • pp.1071-1087
    • /
    • 2017
  • This paper introduces a DC/AC converter, which can be connected in parallel with a diode rectifier for regenerative applications. The DC/AC converter is supposed to transmit regenerative energy to the power grid when a motor is braking. Isolation transformers are not needed in the topology, which can reduce the size and cost. An analysis of the zero-order current existing in the system is carried out. In addition, algorithms to minimize the zero-order current, control the power factor and keep the DC bus voltage stable are discussed. A 55kW industrial prototype is built to verify the proposed analysis and control strategies.

A Study on Micom Algorithm Design for Prevention of Serial Parallel Arc Accident (직병렬아크사고 예방을 위한 마이컴 알고리즘 설계에 관한 연구)

  • Choi, Jung-Kyu;Kwak, Dong-Kurl;Choi, Shin-Hyeong;Jung, Do-Young;Kim, Dae-Hwan
    • Proceedings of the KIPE Conference
    • /
    • 2018.11a
    • /
    • pp.9-11
    • /
    • 2018
  • This paper studies on the development of an electric fire prevention system with the detection and alarm in case of parallel arc fault occurrence in low voltage distribution lines. The proposed detector has the characteristics of high speed operation responsibility and superior system reliability from composition using a large number of semiconductor devices. The line voltage is always feedback, and when an arc or a spark occurs, these are detected by the microcomputer. In addition, we design and develop algorithms using high speed and high precision microcomputer. A new conceptual control technique is adopted that RCD cuts-off by forming a forced short circuit between the phase voltage and ground in the event of an electrical accident. Some experimental tests of the proposed system also confirm practicality and the validity of the analytical results.

  • PDF

Implementation of a Wi-Fi Based Cluster System using Raspberry Pi for Multidisciplinary Education

  • Koo, Geum-Seo;Sim, Gab-Sig
    • Journal of the Korea Society of Computer and Information
    • /
    • v.24 no.1
    • /
    • pp.1-7
    • /
    • 2019
  • In this paper, we implemented a Wi-Fi based cluster system using raspberry pi for multidisciplinary education. The cluster implementation on the desktop was more difficult to maintain the complexity, big size, high price, power consumption as the number of nodes increased. In this paper, we implemented a cluster using Raspberry Pi, which is developed for educational purposes, to reduce the cost of connecting nodes. In addition, the complexity of system construction is reduced by replacing the connection between each node with Wi-Fi. Also, the inconvenience of configuration due to node increase was reduced. It is expected that the implementation of the cluster will be a good alternative in the educational environment where distributed processing and parallel processing are performed in the embedded environment. Also, it is confirmed that it can be applied to the multidisciplinary education.