• Journal of the Korean Society for Precision Engineering
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• v.21 no.1
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• pp.116-123
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• 2004

The demand for the stable and comfortable cabin of a high speed passenger ship is increasing. The study on shipboard comfort has been mainly concentrated on the motion control of a whole hull body. In this study, however, a new control system operated by two parallel robots (3RPS, 3SPR) such as the active suspension system of motor vehicle is proposed. The goal of this control is keeping zero velocity of the upper robot (cabin) although the lower robot (ship) is moving by the waves. Jacobian matrix was used to design the controller, From the simulation results, the remarkable reduction of motion of the cabin (upper platform) was observed. The 3SPR parallel robot shows better performance compared to the 3RPS robot.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.10
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• pp.1672-1681
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• 2016

This paper proposes a wireless parallel operation method of three-phase modular UPS inverter using resistive droop control. Furthermore, it applies a virtual resistor to droop control so that the output impedance of UPS inverter gets closer to resistive. It makes resistive droop control effective. The simulation using PSIM was performed in order to verify the validity of proposed algorithm. After consisting two-parallel system with three-phase modular UPS inverter, the experiment according to resistive load was conducted. It demonstrated the performance of current sharing and power sharing.

• International Journal of Contents
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• v.9 no.1
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• pp.33-37
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• 2013

BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.

• Journal of Power Electronics
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• v.12 no.4
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• pp.595-603
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• 2012

This paper presents a full digital control strategy for parallel connected modular inverter systems. Each modular inverter is a high frequency (HF) AC link inverter which is composed of a HF inverter and a HF transformer followed by a cycloconverter. To achieve equal sharing of the load current and to suppress the circulating currents among the modules, a three-loop control strategy, consisting of a common output voltage regulation (OVR) loop, individual circulating current suppression (CCS) loops and individual inner current tracking (ICT) loops, is proposed. The ICT loops are implemented with predictive current control from which high precision current tracking can be obtained. The effectiveness of the proposed control strategy is verified by simulation and experimental results from parallel connected two full-bridge HF AC link inverter modules.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.378-380
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• 2006

A high speed Analog parallel processing-based Viterbi decoder with a circularly connected 2D analog processing cell array is proposed. It has a 2D parallel processing structure in which an analog processing cell is placed at each node of trellis diagram is connected circulary so that infinitively expanding trellis diagram is realized with the fixed size of circuits. The proposed Viterbi decoder has advantages in that it is operated with better performance of error corrections, has a shorter latency and requires no path memories. In this parer, the performance of error correction as a reference position with the Analog parallel processing-based Viterbi decoder is testd via the software simulation

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.213-216
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• 1996

This paper studies a class of in-parallel manipulators with special geometry where the forward displacement analysis problem can be solved easier than the fully parallel manipulators. Three horizontal links of this mechanism provide 3DOFs(Degrees of Freedom), which are one degree of orientational freedom and two degrees of translatory freedom. Three vertical links of this mechanism provide 3DOFs, which are two degrees of orientational freedom and one degree of translatory freedom. The main advantages of this manipulator, compared with the Stewart platform type, are the capability to produce pure rotation and to predict the motion of the moving platform easily. Since this manipulator has simple kinematic characteristics compared with the Stewart platform, controlling in real-time is possible due to less computational burden. The purpose of this investigation is to develope an analytical method and systematic method to analyze the basic kinematics of the manipulator. The basic kinematic equations of the manipulator are derived and simulation is carried out to show the performance of the mechanism.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.153-156
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• 2002

In this paper, we have designed a small size lumped/distributed hybrid element directional coupler using parallel coupled-line theory. a hybrid lumped equivalent circuit for a conventional parallel directional coupler is proposed. The equivalent circuit and design formula for the presented lumped element coupler are derived based on the even- and odd-mode properties of a parallel-coupled line. By using the derived design formula, we have extracted design parameters and designed the 3㏈ and 10㏈ small size lumped element directional couplers at the center frequency of 2Ghz. Excellent agreements between design theory and simulation on the designed directional couplers show the validity of this paper.

• Journal of Industrial Technology
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• v.21 no.A
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• pp.73-80
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• 2001

Barrier is widely used for synchronization in parallel programs. Since the process arrived earlier than others should wait at the barrier, the total processor utilization decreases. In this paper, to find the sources of the barrier waiting time, parallel programs are executed on the various grain sizes through execution-driven simulations. In simulation studies, we found that even if approximately equal amounts of work are distributed to each processor, all processes may not arrive at a barrier at the same time. The reasons are that the different numbers of cache misses and instructions within partitioned grains result in the difference in arrival time of processors at the barrier.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.1
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• pp.60-68
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• 1998

Parallel link manipulators have an ability of more precise positioning than serial open-loop manipulators. However. general parallel link manipulators have been restricted to the real applications since they have limited workspace due to interference among actuators. In this study, we suggest a closed-loop manipulator with 6 degrees-of-freedom and with enlarged workspace. It consists of two parts for minimizing the interference among actuators. One part is lower structure with planar 3 degrees-of-freedom and the other is upper one with spatial 3 degrees-of-freedom. Forward kinematics and inverse kinematics are solved, research about singularity points are carried out and workspace is evaluated. The comparison of workspace between Stewart platform, which is the typical parallel link manipulator, and the suggested manipulator shows that the workspace of the latter is wider than that of the former. Especially, simulation results also show that the suggested manipulator is more suitable when there needs rotation in the end-effector.

• 한국전산유체공학회:학술대회논문집
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• 2008.03b
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• pp.472-473
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• 2008

Flow boiling in parallel microchannels has received attention as an effective heat sink mechanism for power-densities encountered in microelectronic equipment. the bubble dynamics coupled with boiling heat transfer in microchannels is still not well understood due to the technological difficulties in obtaining detailed measurements of microscale two-phase flows. In this study, complete numerical simulation is performed to further clarify the dynamics of flow boiling in microchannels. The level set method for tracking the liquid-vapor interface is modified to include the effects of phase change and contact angle. The method is further extended to treat the no-slip and contact angle conditions on the immersed solid. Also, the reverse flow observed during flow boiling in parallel microchannels has been investigated. Based on the numerical results, the effects of channel shape and inlet area restriction on the bubble growth, reverse flow and heat transfer are quantified.