• The KIPS Transactions:PartA
• /
• v.8A no.4
• /
• pp.419-428
• /
• 2001

Advances in circuit and integration technology are continuously boosting the speed of processors. One of the main challenges presented by such developments is the effective use of powerful processors in shared memory multiprocessor system. We believe that the interconnection problem is not solved even for small scale shared memory multiprocessor, since the speed of shared buses is unlikely to keep up with the bandwidth requirements of new powerful processors. In the past few years, point-to-point unidirectional connection have emerged as a very promising interconnection technology. The single slotted ring is the simplest form point-to-point interconnection. The main limitation of the single slotted ring architecture is that latency of access increase linearly with the number of the processors in the ring. Because of this, we proposed the dual slotted ring as an alternative to single slotted ring for cache-based multiprocessor system. In this paper, we analyze the proposed dual slotted ring architecture using new snooping protocol and enforce simulation to compare it with single slotted ring.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.16 no.5
• /
• pp.415-429
• /
• 2011

In this study, a single-phase quasi Z-source AC-AC converters with a series connection of the output terminals is proposed. The proposed system has configuration that the input terminals of two quasi Z-source AC-AC converters are connected in parallel and its output terminals are connected in series. The out of phase mode and in phase mode of the proposed system are presented. To verify the validity of the proposed converter, a DSP controlled hardware was made and PSIM simulation was executed. As a result, controlling the duty ratio of the converter, the desired buck-boost output voltages could be generated. For each modes, as compared with the single converter operation, the proposed converter could enhance the efficiency and input power factor according to different loads. Also, in case of the out of phase mode under the constant load, the efficiency and input power factor of the proposed system are increased 10[%], 35[%] respectively in compared with the single converter. And, the output voltage is constantly controlled in dynamic state in case while the load is suddenly changed.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.65 no.8
• /
• pp.1340-1346
• /
• 2016

Utilization of Distributed Generations (DGs) using Renewable Energy Sources (RESs) has been constantly increasing as they provide a lot of environmental, economic merits. In spite of these merits, some problems with respect to voltage profile, protection and its coordination system due to reverse power flow could happen. In order to analyze and solve the problems, accurate modeling of DG systems should be preceded as a fundamental research task. In this paper, we present a PhotoVoltaic (PV) generation system which consists of practical PV cells with series and parallel resistor and an inverter for interconnection with a main distribution system. The inverter is based on controllable current source which is capable of controlling power factors, active and reactive powers within a certain limit related to amount of PV generation. To verify performance of the model, a distribution system based on actual data is modeled by using ElectroMagnetic Transient Program (EMTP) software. Computer simulations according to various conditions are also performed and it is shown from simulation results that the model presented is very effective to study DG-related researches.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.10C
• /
• pp.923-929
• /
• 2003

Turbo processing have been known as methods close to Shannon limit in the aspect of wireless multi-input multi-output (MIMO) communications similarly to wireless single antenna communication. The iterative processing can maximize the mutual effect of coding and interference cancellation, but LDPC coding has not been used for turbo processing because of the inherent decoding process delay. This paper suggests a LDPC coded MIMO system with turbo parallel space-time (Turbo-PAST) processing for high-speed wireless communications and proposes a average soft-output syndrome (ASS) check scheme at low signal to noise ratio (SNR) for the Turbo-PAST system to decide the reliability of decoded frame. Simulation results show that the suggested system outperforms conventional system and the proposed ASS scheme effectively reduces the amount of turbo processing iterations without performance degradation from the point of average number of iterations.

• Journal of the Korean Society of Fisheries and Ocean Technology
• /
• v.31 no.2
• /
• pp.178-189
• /
• 1995

In this pater, authors derive the state - space equiation about the patallel - type inverted pendulum which is adopted as control object, and constitute the control system by $H_\infty$control theory. The modeling error is unavoidably existed by linearization error, and so on. We regard this modeling error which is determined from the identification through frequency response as unstructured model uncertainty. An augmented state - space equiation with frequency weighting function is constructed for application of the $H_\infty$theory, and the mixed sensitivity problem is considered. The weighting functions are determined in consideration of the model uncertainty and the response of system in frequency region. The $H_\infty$controller is designed by using software package for controller design. From results of response simulation, the control system designed with $H_\infty$theory guarantees low sensitivity for disturbance as well as robustness against the model uncertainties.

• Journal of KIISE:Computer Systems and Theory
• /
• v.31 no.5_6
• /
• pp.360-370
• /
• 2004

Adaptive mesh refinement(AMR) is one of the popular computational simulation techniques used in various scientific and engineering fields. Although AMR data is organized in a hierarchical multi-resolution data structure, traditional volume visualization algorithms such as ray-casting and splatting cannot handle the form without converting it to a sophisticated data structure. In this paper, we present a hierarchical multi-resolution splatting technique using k-d trees and octrees for AMR data that is suitable for implementation on the latest consumer PC graphics hardware. We describe a graphical user interface to set transfer function and viewing / rendering parameters interactively. Experimental results obtained on a general purpose PC equipped with an nVIDIA GeForce3 card are presented to demonstrate that the proposed techniques can interactively render AMR data(over 20 frames per second). Our scheme can easily be applied to parallel rendering of time-varying AMR data.

• Journal of Power Electronics
• /
• v.17 no.6
• /
• pp.1658-1671
• /
• 2017

To address the inaccurate load demand sharing problems among parallel inverter-interfaced voltage-controlled distributed generation (DG) units in islanded microgrids (MGs) with different DG power ratings and mismatched feeder impedances, an enhanced voltage control scheme based on the active compensation of circulating voltage drops is proposed in this paper. Using the proposed strategy, reactive power and harmonic currents are shared accurately and proportionally without knowledge of the feeder impedances. Since the proposed local controller consists of two well-separated fundamental and harmonic voltage control branches, the reactive power and harmonic currents can be independently shared without having a remarkable effect on the amplitude or quality of the DGs voltage, even if nonlinear (harmonic) loads are directly connected at the output terminals of the units. In addition, accurate load sharing can also be attained when the plug-and-play performance of DGs and various loading conditions are applied to MGs. The effects of communication failures and latency on the performance of the proposed strategy are also explored. The design process of the proposed control system is presented in detail and comprehensive simulation studies on a three-phase MG are provided to validate the effectiveness of the proposed control method.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.6
• /
• pp.1056-1063
• /
• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decoder is parameterized for the code rates 1/2, 1/3 and constraint lengths 7,9, thus it has four operation nodes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency. Also, the simulation results for BER (Bit Error Rate) performance show that the Viterbi decoder has BER of $10^{-4}$ at $E_b/N_o$ of 3.6 dB when it operates with code rate 1/3 and constraints 7.

• Journal of Korea Water Resources Association
• /
• v.52 no.11
• /
• pp.887-894
• /
• 2019

We proposed a GPU (Grapic Processing Unit) accelerated kinematic wave model for rainfall runoff simulation and tested the accuracy and speed up performance of the proposed model. The governing equations are the kinematic wave equation for surface flow and the Green-Ampt model for infiltration. The kinematic wave equations were discretized using a finite volume method and CUDA fortran was used to implement the rainfall runoff model. Several numerical tests were conducted. The computed results of the GPU accelerated kinematic wave model were compared with several measured and other numerical results and reasonable agreements were observed from the comparisons. The speed up performance of the GPU accelerated model increased as the number of grids increased, achieving a maximum speed up of approximately 450 times compared to a CPU (Central Processing Unit) version, at least for the tested computing resources.

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.38 no.4
• /
• pp.159-167
• /
• 2015

We consider a wafer lot transfer/release planning problem from semiconductor wafer fabrication facilities to probing facilities with the objective of minimizing the deviation of workload and total tardiness of customers' orders. Due to the complexity of the considered problem, we propose a two-level hierarchical production planning method for the lot transfer problem between two parallel facilities to obtain an executable production plan and schedule. In the higher level, the solution for the reduced mathematical model with Lagrangian relaxation method can be regarded as a coarse good lot transfer/release plan with daily time bucket, and discrete-event simulation is performed to obtain detailed lot processing schedules at the machines with a priority-rule-based scheduling method and the lot transfer/release plan is evaluated in the lower level. To evaluate the performance of the suggested planning method, we provide computational tests on the problems obtained from a set of real data and additional test scenarios in which the several levels of variations are added in the customers' demands. Results of computational tests showed that the proposed lot transfer/planning architecture generates executable plans within acceptable computational time in the real factories and the total tardiness of orders can be reduced more effectively by using more sophisticated lot transfer methods, such as considering the due date and ready times of lots associated the same order with the mathematical formulation. The proposed method may be implemented for the problem of job assignment in back-end process such as the assignment of chips to be tested from assembly facilities to final test facilities. Also, the proposed method can be improved by considering the sequence dependent setup in the probing facilities.