• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• Journal of Sensor Science and Technology
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• v.23 no.6
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• pp.368-376
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• 2014

In order to measure the segmental impedance of the body, a bioelectrical impedance measurement system (BIMS) using multi-frequency applying method and two-electrode method was implemented in this study. The BIMS was composed of constant current source, automatic gain control, and multi-frequency generation units. Three experiments were performed using the BIMS and a commercial impedance analyzer (CIA). First, in order to evaluate the performance of the BIMS, four RC circuits connected with a resistor and capacitor in serial and/or parallel were composed. Bioelectrical impedance (BI) was measured by applying multi-frequencies -5, 10, 50, 100, 150, 200, 300, 400, and 500 KHz - to each circuit. BI values measured by the BIMS were in good agreement with those obtained by the CIA for four RC circuits. Second, after measuring BI at each frequency by applying multi-frequency to the left and right forearm and the popliteal region of the body, BI values measured by the BIMS were compared to those acquired by the CIA. Third, when the distance between electrodes was changed to 1, 3, 5, 7, 9, 11, 13, and 15 cm, BI by the BIMS was also compared to BI from the CIA. In addition, BI of extracellular fluid (ECF) was measured at each frequency ranging from 10 to 500 KHz. BI of intracellular fluid (ICF) was calculated by subtracting BI of ECF measured at 500 kHZ from BI measured at seven frequencies ranging from 50 to 500 KHz. BI of ICF and ECF decreased as the frequency increased. BI of ICF sharply decreased at frequencies above 300 KHz.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1305-1317
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• 2015

Distributed generation systems (DGSs) have been getting more and more attention in terms of renewable energy use and new generation technologies in the past decades. The self-excited induction generator (SEIG) occupies an important role in the area of energy conversion due to its low cost, robustness and simple control. Unlike synchronous generators, the SEIG has to absorb capacitive reactive power from the outer device aiming to stabilize the terminal voltage at load changes. This paper presents a novel static VAR compensator (SVC) called a magnetic energy recovery switch (MERS) to serve as a voltage controller in SEIG powered DGSs. In addition, many small scale SEIGs, instead of a single large one, are applied and devoted to promote the generation efficiency. To begin with, an expandable mathematic model based on a d-q equivalent circuit is created for parallel SEIGs. The control method of the MERS is further improved with the objective of broadening its operating range and restraining current harmonics by parameter optimization. A hybrid control strategy is developed by taking both of the stand-alone and grid-connected modes into consideration. Then simulation and experiments are carried out in the case of single and double SEIG(s) generation. Finally, the measurement results verify that the proposed DGS with SVC-MERS achieves a better stability and higher feasibility. The major advantages of the mentioned variable reactive power supplier, when compared to the STATCOM, include the adoption of a small DC capacitor, line frequency switching, simple control and less loss.

• Journal of Korea Spatial Information System Society
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• v.6 no.1 s.11
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• pp.3-17
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• 2004

With the rapid growth of the Internet geographic information services through the WWW such as a location-based service and so on. Web GISs (Geographic Information Systems) have also come to be a cluster-based architecture like most other information systems. That is, in order to guarntee high quality of geographic information service without regard to the rapid growth of the number of users, web GISs need cluster-based architecture that will be cost-effective and have high availability and scalability. This paper proposes the design of the cluster-based web GIS with high availability and scalability. For this, each node within a cluster-based web GIS consists of main memory spatial databases which accomplish role of caching by using data declustering and the locality of spatial query. Not only simple region queries but also the proposed system processed spatial join queries effectively. Compare to the existing method. Parallel R-tree spatial join for a shared-Nothing architecture, the result of simulation experiments represents that the proposed spatial join method achieves improvement of performance respectively 23% and 30% as data quantity and nodes of cluster become large.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.7
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• pp.10-16
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• 1999

This paper describes a low voltage swing bus driver using FCSR(Feedback Control Swing voltage Reduction) which can control bus swing voltage within a few hundred of mV. It is proposed to reduce power consumption in On-chip interface, especially for MDL(Merged DRAM Logic) architecture wihich has wide and large capacitance bus. FCSR operates on differential signal dual-line bus and on precharged bus with block controlling fuction. We modeled driver and bus to scale driver size automatically when bus environment is variant. We also modeled coupling capacitance noise(crosstalk) of neighborhood lines which operate on odd mode with parallel current source to analysis crosstalk effect in the victim-line according as voltage transition in the aggressor-line and environment in the victim-line. We built a test chip which was designed to swing 600mV in bus, shows 70Mhz operation at 3.3V, using Hyundai 0.8um CMOS technology. FCSR operate with 250Mhz at 3.3V by Hspice simulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.67-75
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• 2013

In this paper, an analytical model is presented for the source/drain parasitic resistance of FinFET. The parasitic resistance is a important part of a total resistance in FinFET because of current flow through the narrow fin. The model incorporates the contribution of contact and spreading resistances considering three-dimensional current flow. The contact resistance is modeled taking into account the current flow and parallel connection of dividing parts. The spreading resistance is modeled by difference between wide and narrow and using integral. We show excellent agreement between our model and simulation which is conducted by Raphael, 3D numerical field solver. It is possible to improve the accuracy of compact model such as BSIM-CMG using the proposed model.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.11
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• pp.1429-1436
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• 1999

데이타들에 대한 선인출 효과를 얻기 위하여 캐쉬 메모리의 캐쉬 블록은 다중 워드로 구성된다. 그러나 선인출된 데이타들이 사용되지 않을 경우 캐쉬 메모리가 낭비되고 따라서 캐쉬 실패율이 증가한다. 데이타 배열 병합 방법은 캐쉬 실패 원인의 하나인 캐쉬 충돌 실패를 감소시키기 위하여 사용되고 있다. 그러나 기존의 배열 병합 방법은 유용하지 못한 데이타들을 캐쉬 블록에 선인출하는 현상을 보인다. 본 논문에서는 이러한 현상을 개선한 스트라이드 배열 병합을 제안한다. 모의시험에서 캐쉬 블록이 다중 워드로 구성된 경우 스트라이드 배열 병합은 캐쉬 충돌 실패를 감소시킬 뿐 만 아니라 유용한 데이타 선인출을 증가 시키므로 캐쉬 성능을 향상시킴을 보여준다. 또한 이렇게 향상된 캐쉬 성능은 프로세서 증가에 따른 확장성 있는 프로그램 성능을 나타낸다.Abstract The cache memory is composed of cache lines with multiple words to achieve the effect of data prefetching. However, if the prefetched data are not used, the spaces of the cache memory are wasted and thus the cache miss rate increases. The data merging-arrays method is used for the sake of the reduction of the cache conflict misses. However, the existing merging-arrays method results in the useless data prefetching. In this paper, a stride merging-arrays method is suggested for improving this phenomenon. Simulation results show that when a cache line is composed of multiple words, the stride merging-arrays method increases the cache performance due to not only the reduction of cache conflict misses but also the useful data prefetching. This enhanced cache performance also represents the more scalable performance of parallel applications according to increasing the number of processors.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.1045-1049
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• 2005

In this paper, the dynamic crawling of a five-bar planar mechanism is investigated. One complete cycle of the crawling selected in this study consists of four different steps, i) sliding at one contact point between the mechanism and the ground, ii) changing its configuration without sliding at two contact points, iii) sliding at the other contact point, and iv) again changing its configuration without sliding at two contact points. In this type of crawling, the crawling mechanism maintains the shape of the parallel structure throughout a complete crawling cycle. The modeling algorithm for serial manipulators proposed by M. Thomas and et al.[1] is employed by introducing imaginary joints and links which represent the contact interfaces between the one end of the mechanism and the ground, while the other end of the mechanism is regarded as an end-effector of the imaginary serial manipulator which treats the reaction force and torque at the contact point as external forces. Then, a complete cycle of dynamic crawling of the mechanism is investigated through various computer simulations. The simulation result show that the stable crawling characteristics of the mechanism could be secured when the proper configurations depending on specified frictional constraints are met.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.4
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• pp.1-8
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• 2005

Plasma researches using parallel-plate electrodes are widely used in semiconductor application such as etching and thin film deposition. Therefore, a quantitative understanding and control of plasma behavior are becoming increasingly necessary because their important applications and simulation techniques have been actively carried out in order to solve such problems above. In this paper, we developed a two-dimensional(2D) self-consistent fluid model, because 2D models can deal with real reactor geometries. The fluid model is based on particle continuity equations for taking account of an electrode system in a cylindrical geometry. An pure Ar gas was used at 500[mTorr] and radio-frequency (13.56(MHz)). Four models were simulated under the different electrode geometries which have chamber widths of 5.25, 6.0, 8.0, and 10.0[cm] and we compared their results with each other. Plasma uniformity and a do self-bias voltage were also discussed.

• The KIPS Transactions:PartA
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• v.17A no.3
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• pp.121-126
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• 2010

This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The $16{\times}16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung $0.18\;{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.