• Industrial Engineering and Management Systems
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• v.4 no.2
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• pp.117-122
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• 2005

An assembly system (AS), a valuable tool for mass production, is generally composed of a number of workstations and a transport system. While the workstations perform some preplanned operations, the transport system moves the assemblies by special designed pallets from one station to another. One common problem associated with automatic assembly systems is that some assembly operations may have relatively long cycle times. As a consequence, the productivity, as determined by the operations with the longest cycle time, can be reduced significantly. Therefore, special forms of parallel workstations were developed to improve the performance of an assembly system. In this paper, three most commonly used parallel stations: on-line, off-line and tunnel-gated stations in a free transfer assembly system are studied via discrete event simulation. Our findings revealed that the off-line parallel system has the best performance because the two independent parallel stations can lower the buffer requirement; reduce the sensitivity to variability of processing time and balance of a line. On-line parallel systems were found to have a relatively poor performance, because the operations of two parallel stations block each other, and higher buffer capacity is required to achieve similar capacity. The tunnel-gated system was more efficient than the on-line system since the first parallel station can operate independently. More importantly, we have quantified the productivity of the three different strategies mentioned. Engineers can choose the optimal strategies for installing parallel stations under their working environment.

• Journal of the Korean Operations Research and Management Science Society
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• v.18 no.3
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• pp.13-34
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• 1993

By operating on many part of a software system concurrently, the parallel processing computers may provide several orders of magnitude more computing power than traditional serial computers. If the Lagrangean approximation procedure is applied to a large scale manufacturing problem which is decomposable into many subproblems, the procedure is a perfect candidate for parallel processing. By distributing Lagrangean subproblems for given multiplier to multiple processors, concurrently running processors and modifying Lagrangean multipliers at the end of each iteration of a subgradient method,a parallel processing of a Lagrangean approximation procedure may provide a significant speedup. This purpose of this research is to investigate the potential of the parallelized Lagrangean approximation procedure (PLAP) for certain combinational optimization problems in manufacturing systems. The framework of a Plap is proposed for some combinatorial manufacturing problems which are decomposable into well-structured subproblems. The synchronous PLAP for the multistage dynamic lot-sizing problem is implemented on a parallel computer Alliant FX/4 and its computational experience is reported as a promising application of vector-concurrent computing.

• Journal of Mechanical Science and Technology
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• v.19 no.11
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• pp.2007-2015
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• 2005

A large-scale analysis to evaluate complex material and structural behaviors is one of interesting topic in diverse engineering and scientific fields. Also, the utilization of massively parallel processors has been a recent trend of high performance computing. The objective of this paper is to introduce a parallel process system which consists of general purpose finite element analysis solver as well as parallelized PC cluster. The later was constructed using eight processing elements and the former was developed adopting both hierarchical domain decomposition method and balancing domain decomposition method. Then, to verify the efficiency of the established system, it was applied for structural analysis of steam generator in nuclear power plant. Since the prototypal evaluation results agreed well to the corresponding reference solutions it is believed that, after reinforcement of PC cluster by increasing number of processing elements, the promising parallel process system can be utilized as a useful tool for advanced structural integrity evaluation.

• Journal of Industrial Technology
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• v.10
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• pp.15-20
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• 1990

A parallel processing algorithm for discrete Kalman filter, which is one of the most commonly used filtering technique in modern control, signal processing, and communication, is proposed. Previously proposed parallel algorithms to decrease the number of computations needed in the Kalman filter are the hierachical structures by distributed processing of measurements, or the systolic structures to disperse the computational burden. In this paper, a new parallel Kalman filter employing a structure similar to recursive doubling is proposed. Estimated values of state variables by the new algorithm converge with two times faster data processing speed than that of the conventional Kalman filter. Moreover it maintains the optimality of the conventional Kalman filter.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.64-67
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• 1990

A parallel processing algorithm for discrete Kalman filter, which is one of the most commonly used filtering technique in modern control, signal processing, and communication. is proposed. Previously proposed parallel algorithms to decrease the number of computations needed in the Kalman filter are the hierachical structures by distributed processing of measurements, or the systolic structures to disperse the computational burden. In this paper, a new parallel Kalman filter employing a structure similar to recursive doubling is proposed. Estimated values of state variables by the new algorithm converge with two times faster data processing speed than that of the conventional Kalman filter. Moreover it maintains the optimality of the conventional Kalman filter.

• Proceedings of the KSR Conference
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• 2004.10a
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• pp.1235-1240
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• 2004

This paper has presented the parallel cyclic redundancy check (CRC) technique that performs CRC computation in parallel superior to the conventional CRC technique that processes data bits serially. Also, it has showed that the implemented parallel CRC circuit had been successfully applied to the inductively coupled passive RFID system working at a frequency of 13.56MHz in order to process the detection of logical faults more fast and the system had been verified experimentally. In comparison with previous works, the proposed RFID system using the parallel CRC technique has been shown to reduce the latency and increase the data processing rates in the results. Therefore, it seems reasonable to conclude that the parallel CRC realization in the RFID system offers a means of maintaining the integrity of data in the high speed RFID system.

• Journal of the Korea Society of Computer and Information
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• v.18 no.1
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• pp.1-10
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• 2013

In this paper, we propose a CUDA(Common Unified Device Architecture) based SW(software) design method for CPU(Central Processing Unit) and GPU(Graphic Processing Unit) parallel structure to implement real-time process in 3D Laser ladar(LADAR) imaging system. LADAR is a complex system to generate 3-dimensional image based on the laser ranging information, and requires massive process resources in each phase. Therefore, designing and implementing parallel structure are crucial to realize a real-time process within limited system resource. As a conclusion, we can meet the speed of required real-time process allocating separable work load to CUDA GPU by analyzing process algorithm in each phase and confirm the process speed increase by 46%.

• The Transactions of the Korea Information Processing Society
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• v.3 no.4
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• pp.766-780
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• 1996

This paper presents a mapping scheme for parallel processing using an accurate characterization of the communication overhead. A set of objective functions is formulated to evaluate the optimality of mapping a problem graph into a system graph. One of them is especially suitable for real-time applications of parallel processing. These objective functions are different from the conventional objective functions in that the edges in the problem graph are weighted and the actual distance rather than the nominal distance for the edges in the system graph is employed. This facilitates a more accurate qualification of the communication overhead. An efficient mapping scheme has been developed for the objective functions, where two levels of assignment optimization procedures are employed: initial assignment and pairwise exchange. The mapping scheme has been tested using the hypercube as a system graph.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.6
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• pp.161-169
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• 2011

Recent intelligent video surveillance system asks for development of more advanced technology for analysis and recognition of video data. Especially, machine learning algorithm such as Support Vector Machine (SVM) is used in order to recognize objects in video. Because SVM training demands massive amount of computation, parallel processing technique is necessary to reduce the execution time effectively. In this paper, we propose a parallel processing method of SVM training with a multi-core processor. The results of parallel SVM on a 4-core processor show that our proposed method can reduce the execution time of the sequential training by a factor of 2.5.

• Journal of the Korea Society of Computer and Information
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• v.11 no.4 s.42
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• pp.35-45
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• 2006

RIn this paper. we describe real-time parallel processing simulator developed for the use of performance analysis of rolling missiles. The real-time parallel processing simulator developed here consists of seeker emulator generating infrared image signal on aircraft, real-time computer, host computer, system unit, and actual equipments such as auto-pilot processor and seeker processor. Software is developed according to the design requirements of mathematic model, 6 degree-of-freedom module, aerodynamic module which are resided in real-time computer. and graphic user interface program resided in host computer. The real-time computer consists of six TI C-40 processors connected in parallel. The seeker emulator is designed by using analog circuits coupled with mechanical equipments. The system unit provides interface function to match impedance between the components and processes very small electrical signals. Also real launch unit of missiles is interfaced to simulator through system unit. In order to use the real-time parallel processing simulator developed here as a performance analysis equipment for rolling missiles, we perform verification test through experimental results in the field.