• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.429-432
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• 2000

The new MPEG-4 video coding standard enables content-based functionalities. In order to support the philosophy of the MPEG-4 visual standard, each frame of video sequences should be represented in terms of video object planes (VOP’s). In other words, video objects to be encoded in still pictures or video sequences should be prepared before the encoding process starts. Therefore, it requires a prior decomposition of sequences into VOP’s so that each VOP represents a moving object. A parallel processing system is required an automatic segmentation to be processed in real-time, because an automatic segmentation is time consuming. This paper addresses the parallel processing: system for an automatic segmentation for separating moving object from the background in image sequences. The proposed parallel processing system comprises of processing elements (PE’s) and a multi-access memory system (MAMS). Multi-access memory system is a memory controller to perform parallel memory access with the variety of types: horizontal, vertical, and block access way. In order to realize these ways, a multi-access memory system consists of a memory module selection module, data routing modules, and an address calculation and routing module. The proposed system is simulated and evaluated by the CADENCE Verilog-XL hardware simulation package.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.149-151
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• 2002

We had been developing the variety of parallel processing systems in order to improve the processing speed of visual media applications. These systems were using multi-access memory system(MAMS) as a parallel memory system, which provides the capability of the simultaneous accesses of image points in a line-segment with an arbitrary degree, which is required in many low-level image processing operations such as edge or line detection in a particular direction, and so on. But, the performance of these systems did not give a faithful speed because of asynchronous feature between MAMS and processing elements. To improve the processing speed of these systems, we have been investigated a pipelined parallel processing system using MAMS. Although the system is considered as being the single instruction multiple data(SIMD) type like the early developed systems, the performance of the system yielded about 2.5 times faster speed.

• 한국경영과학회지
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• 제39권4호
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• pp.19-31
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• 2014

We study parallel processing techniques for the R programming language of high performance computing technology. In this study, we used massively parallel computing system which has 25,408 cpu cores. We conducted a performance evaluation of a distributed memory system using MPI and of a the shared memory system using OpenMP. Our findings are summarized as follows. First, For some particular algorithms, parallel processing is about 150 times faster than serial processing in R. Second, the distributed memory system gets faster as the number of nodes increases while shared memory system is limited in the improvement of performance, due to the limit of the number of cpus in a single system.

• 정보처리학회논문지A
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• 제11A권3호
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• pp.181-188
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• 2004

인터넷 기반 분산/병렬 처리 시스템인 PDP(Parallel/Distributed Processing)는 인터넷의 유휴상태 호스트들을 이용하여 대용량 작업을 병렬로 처리해서 전체 수행 시간을 감소시킨다. 본 연구에서는 실시간 네트워크 모니터링을 활용하여 수시로 변화하는 네트워크 환경에 적응하여 병렬/분산 처리되는 방안을 제안한다. 실시간 네트워크 모니터링 정보를 PDP 주요 핵심 알고리즘들에 적용하여 네트워크 과부하 및 결함으로 발생하는 작업 지연 요소에 적응적으로 대처함으로써 전체 성능이 향상됨을 보인다.

• 한국전산구조공학회:학술대회논문집
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• 한국전산구조공학회 2001년도 봄 학술발표회 논문집
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• pp.61-68
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• 2001

A parallel nonlinear analysis program of prestressed concrete frame is migrated on a PC cluster system and a massively parallel processing system, CRAY T3E system, using MPI. The PC cluster system is configured with Pentium Ⅲ class PCs and fast ethernet. The CRAY T3E system is composed of a set of nodes each containing one Processing Element (PE), a memory subsystem and its distributed memory interconnect network. Parallel computing algorithms are implemented on element-wise processing parts including the calculation of stiffness matrix, element stresses and determination of material states, check of material failure and calculation of unbalanced loads. Parallel performance of the migrated program is evaluated through typical numerical examples.

• 지능정보연구
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• 제6권1호
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• pp.113-128
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• 2000

This paper presents a first year report of an ongoing multi-year project to develop a systolic parallel simulation system for dynamic traffic assignment. The fundamental approach to the simulation is systolic parallel processing based on autonomous agent modeling. Agents continuously act on their own initiatives and access to database to get the status of the simulation world. Various agents are defined in order to populate the simulation world. In particular existing modls and algorithm were incorporated in designing the behavior of relevant agents such as car-following model headway distribution Frank-Wolf algorithm and so on. Simulation is based on predetermined routes between centroids that are computed off-line by a conventional optimal path-finding algorithm. Iterating the cycles of optimization-then-simulation the proposed system will provide a realistic and valuable traffic assignment. Gangnum-Gu district in Seoul is selected for the target are for the modeling. It is expected that realtime traffic assignment services can be provided on the internet within 3 years.

• 정보처리학회논문지A
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• 제10A권2호
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• pp.111-122
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• 2003

군사용 워게임 시뮬레이션 모델들의 상호연동을 위해서는 국제표준연동(HLA : High Level Architecture)구조를 반드시 갖추어야하며 타 모델과 연동시 발생되는 시스템 오버헤드를 줄이기 위해서는 병렬 시뮬레이션 엔진 도입이 효과적이다. 그러나 기존 군사용 워게임 시뮬레이션 모델엔진의 이벤트 처리는 순차적 이벤트-드리븐 방식으로 처리하고 있다. 이는 병렬로 처리 시 글로벌 자료영역에 대한 동시참조등의 문제점들이 발생하기 때문이다. 아울러 기존 시뮬레이션 플랫폼으로 다중 CPU 시스템을 사용하여도 여러 개의 CPU를 다 활용하지 못하는 결과를 초래하고 있다. 따라서 이 논문에서는 군사용 워 게임 모델의 시스템 처리능력 향상과 글로벌 자료 영역에 대한 동시참조, 대외적인 시뮬레이션 시간처리, 장애 회복(Crash Recovery)시 병행 처리된 이벤트들의 순서를 보장 할 수 있는 객체모델에 기반한 병렬 시뮬레이션 엔진으로의 전환을 제안한다 이 전환된 병렬 시뮬레이션 엔진은 다중 CPU 시스템(SMP)상에서도 병렬 실행이 가능하도록 설계하고 구현하였다.

• 디지털산업정보학회논문지
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• 제9권4호
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• pp.59-67
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• 2013

Compared to the conventional Hardware-oriented base stations, Software Defined Radio (SDR)-based base station provides various advantages especially in flexibility and expandability. It enables the multimode capability required in 4th-generation (4G) environment which aims at a convergence network of various kinds of communication standards. However, since a single base station processes all data required in various multiple waveforms, the SDR base station faces a problem of data processing speed. In this paper, we propose a new concept of SDR base station system which adopts a parallel processing technology of clustering environment. We implemented a WiMAX system with SDR concept which adopts the Message Passing Interface (MPI) technology which enables the speed-up operations. In order to maximize the efficiency of parallel processing in signal processing, we analyze how the algorithm at each of modules is related to data to be processed. Through the implemented system, we show a drastic improvement in operation time due to parallel processing using the proposed MPI technology. In addition, we demonstrate a feasibility of SDR system for 4G or even beyond-4G as well.

• 전자공학회논문지B
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• 제30B권5호
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• pp.120-128
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• 1993

In this paper, an implementation of high-speed parallel processing system for neural network design on the multicomputer network is presented. Linear speedup expandability is increased by reducing the synchronization penalty and the communication overhead. Also, we presented the parallel processing models and their performance evaluation models for each of the parallization methods of the neural network. The results of the experiments for the character recognition of the neural network bases on the proposed system show that the proposed approach has the higher linear speedup expandability than the other systems. The proposed parallel processing models and the performance evaluation models could be used effectively for the design and the performance estimation of the neural network on the multicomputer network.

• 전자공학회논문지B
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• 제29B권1호
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• pp.11-17
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• 1992

This paper is to propose an analytical queuing model for parallel processing of sequential program with nested loops. The analytical results are compared with the results from the implemented multiprocessor system composed of four intel 8088 microprocessor, eight 2KB shared common memories, and a hardware token ring. At results, this study shows that the processed results are almost similar in proposed analytical model and real system. Proposed analytical model can be applied to evaluate parallel processing of sequential program with nested loops.