• Advances in robotics research
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• v.1 no.2
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• pp.141-154
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• 2014

Redundant parallel manipulators have some advantages over the nonredundant parallel manipulators. It is important to determine how many additional branches should be introduced. This paper studies whether one or two additional branches should be added to a 3-DOF parallel manipulator by comparing the flexible deformation of a 3-DOF parallel manipulator with one additional branch and that with two additional branches. The kinematic and dynamic models of the redundant parallel manipulator are derived and the flexible deformation is investigated. The flexible deformation of the manipulators with one additional branch and two branches is simulated and compared. This paper is helpful for designers to design a redundantly actuated parallel manipulator.

• Journal of Multimedia Information System
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• v.4 no.4
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• pp.219-224
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• 2017

This paper is to introduce an application of face recognition algorithm in parallel. We have experiments of 25 images with different motions and simulated the image recognitions; grouping of the image vectors, image normalization, calculating average image vectors, etc. We also discuss an analysis of the related eigen-image vectors and a parallel algorithm. To develop the parallel algorithm, we propose a new type of initial matrices for eigenvalue problem. If A is a symmetric matrix, initial matrices for eigen value problem are investigated: the "optimal" one, which minimize ${\parallel}C-A{\parallel}_F$ and the "super optimal", which minimize ${\parallel}I-C^{-1}A{\parallel}_F$. In this paper, we present a general new approach to the design of an initial matrices to solving eigenvalue problem based on the new optimal investigating C with preserving the characteristic of the given matrix A. Fast all resulting can be inverted via fast transform algorithms with O(N log N) operations.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.5
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• pp.41-51
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• 1996

In this paper, anew parallel processing system based on a cluster architecture which provides scalability of a parallel processing system while maintains shared memory multiprocessor characteristics is proposed. In recent days low cost, high performnce microprocessors have led to construction of large scale parallel processing systems. Such parallel processing systems provides large scalability but are mainly used for scientific applications which have large data parallelism. A shared memory multiprocessor system like TICOM is currently used as aserver for the commercial application, however, the shared memory multiprocessor system is known to have very limited scalability. The proposed architecture can support scalability and performance of the parallel processing system while it provides adaptability for the commerical application, hence it can overcome the limitation of the shared memory multiprocessor. The architecture and characteristics of the proposed system shall be described. A proprietary hierarchical crsossbar network is designed for this system, of which the protocol, routing and switching technique and the signal transfer technique are optimized for the proposed architecture. The design trade-offs for the network are described in this paper and with simulation usihng the SES/workbench, it is explored that the network fits to the proposed architecture.

• ETRI Journal
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• v.32 no.4
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• pp.493-502
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• 2010

The operation time of an encoder is one of the critical implementation issues for satisfying the timing requirements of Long Term Evolution (LTE) systems because the encoder is based on binary operations. In this paper, we propose a design and implementation of a latency efficient encoder for LTE systems. By virtue of 8-bit parallel processing of the cyclic redundancy checking attachment, code block (CB) segmentation, and a parallel processor, we are able to construct engines for turbo codings and rate matchings of each CB in a parallel fashion. Experimental results illustrate that although the total area and clock period of the proposed scheme are 19% and 6% larger than those of a conventional method based on a serial scheme, respectively, our parallel structure decreases the latency by about 32% to 65% compared with a serial structure. In particular, our approach is more latency efficient when the encoder processes a number of CBs. In addition, we apply the proposed scheme to a real system based on LTE, so that the timing requirement for ACK/NACK transmission is met by employing the encoder based on the parallel structure.

• Journal of Power Electronics
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• v.15 no.2
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• pp.327-337
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• 2015

This study discusses the design of a parallel-operated DC-DC single-ended primary-inductor converter (SEPIC) for low-voltage application and current sharing with a constant output voltage. A coupled inductor is used for parallel-connected SEPIC topology. Generally, two separate inductors require different ripple currents, but a coupled inductor has the advantage of using the same ripple current. Furthermore, tightly coupled inductors require only half of the ripple current that separate inductors use. In this proposed work, tightly coupled inductors are used. These produce an output that is more efficient than that from separate inductors. Two SEPICs are also connected in parallel using the coupled inductors with a single common controller. An analog control circuit is designed to generate pulse width modulation (PWM) signals and to fulfill the closed-loop control function. A stable output current-sharing strategy is proposed in this system. An experimental setup is developed for a 18.5 V, 60 W parallel SEPIC (PSEPIC) converter, and the results are verified. Results indicate that the PSEPIC provides good response for the variation of input voltage and sudden change in load.

• Journal of the Korean Society for Precision Engineering
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• v.30 no.10
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• pp.1069-1077
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• 2013

These days, the interest of high speed robotic system is increasing because it is very important to get the cost-competitiveness. The parallel kinematic mechanism is more useful than the serial kinematic mechanism. For the reason, the researches on the parallel robot system as a high speed robotic one are have been done by many researchers. In this paper, the research on the design and analysis of the high speed parallel robot has been done by the authors. First, Basic robot structure is designed and modal analysis is studied to get the basic characteristics of the vibrational motion. Second, the harmonic analysis is studied to get the information of the natural frequency in some different designs of the outer-arm of the parallel robot. Finally, actual robot system is designed and implemented and it is confirmed that the analysis results coincide with the experimental results.

• ETRI Journal
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• v.13 no.2
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• pp.34-41
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• 1991

In this paper, a new distributed parallel algorithm for pattern classification based upon Self-Organizing Neural Network(SONN)[10-12] is developed. This system works without any information about the number of clusters or cluster centers. The SONN model showed good performance for finding classification information, cluster centers, the number of salient clusters and membership information. It took a considerable amount of time in the sequential version if the input data set size is very large. Therefore, design of parallel algorithm is desirous. A new distributed parallel algorithm is developed and experimental results are presented.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.04a
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• pp.585-590
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• 1995

This paper describes strain distribution analysis of a multiple parallel plate structure for a multi-componenet force and moment sensor. A parallel plate structure which has higher rigidity than a simple beam structure are widely used for multi-component force and moment sensor. The strain distribution in the beams of a parallel plate structure should be accurately calculated to design a high precision multi-component force and moment sensor. We derived equations to calculate the strains for multiple parallel plate structure. It reveals that results from finite element analysis and experiment are in good agreement with results from the derived equations.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2000.04b
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• pp.466-473
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• 2000

Optimality Criteria algorithm based on the derivation of reciprocal approximations has been applied to structural optimization of large-scale structures. However, required computational cost for the serial analysis algorithm of large-scale structures consisting of a large number of degrees of freedom and members is too high to be adopted in the solution process of O.C. algorithm Thus, parallel version of O.C. algorithm on the network of personal computers is presented in this Paper. Parallelism in O.C. algorithm may be classified into two regions such as analysis and optimizer part As the first step of development of parallel algorithm, parallel structural analysis algorithm is developed and used in O.C. algorithm The algorithm is applied to optimal design of a 54-story plane frame structure

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.6
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• pp.12-17
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• 2000

IN induction heating system the high frequency operation allows a rapid response to current fluctuation in the inverter and result in improved welding quality. To work induction heating of nonferrous metals, a welding power supply is need high working frequency and high power. This paper is shown design technique for increasing working frequency in induction heating for welding coppers. A series-parallel resonate inverter consists of H-type bridges, each of whose arms is composed of a combination of two parallel IGBTs. Inverter operating with the fixed frequency is controlled by pulse width modulation (PWM). As switching adapted the Zero-Voltage Switching technique to reduce switching losses the system is high efficiency. The propose inverter has feature which is high efficiency for very wide load variations with a narrow range of duty cycle ratio control and load short circuit capability. Detailed experimental results obtained from a 48[V] output, 500[W] experimental inverter are presented to verify the concept.