• Journal of the Korean Institute of Telematics and Electronics
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• v.4 no.4
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• pp.13-18
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• 1967

Since all the poles of the open circuit voltage transfer function of the trigonometric, linear, passive RC circuits exist on the negative real axis of s-plane, its transient response to the unit step input is monotonic. This satisfies the necessary conditions for the applicability of Elmore's method which had been developed originally for the transient analysis of lumped circuit in computing the rise time and delay time of the trigonometric distributed RC circuits. This paper describes the computing method of rise and delay times of the trigonometric distributed RC circuit. The analysis shows that the transient response of this kind circuit depends only upon the time constant and distance angle $\theta$. As $\theta$ is increased, the rise and delay titles are increased non-linearly.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.96-104
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• 2000

This paper presents a simple method to estimate short-circuit power dissipation for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution. The proposed analytical expressions can be easily applied in such applications as power estimation even when the current expression is changed.

• Proceedings of the KSR Conference
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• 2000.11a
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• pp.704-711
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• 2000

This study is carried out using a circuit model approach. First, the self and shunt impedances of all the conductors in the rail system and the mutual impedances between different conductors are computed. Then, a circuit representing the both rail systems at interfaces including the rails, feeders, protection wires, contact wires, ground wires is built. Auto-transformers in the system are also represented in the circuit model. The circuit model is then 1]recessed using a circuit solver based on a double-elimination method. Several different scenarios are analyzed, including the load conditions and a few fault conditions with different fault locations. The effect of the buried ground wires is also analyzed by comparing the results with and without the presence of the ground wires. The analysis procedure presented in the paper demonstrated an accurate way of computing fault current distribution and EMC at interfaces between both systems. The results presented in the paper can be used as a reference for estimating interference levels in similar rail systems.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.1
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• pp.10-15
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• 1990

This paper presents an algorithm that can compute equivalent impedance effctively in computing 3-phase short circuit current which would be generated in power systems. Also this paper proposes a method that can decide the capacity of circuit breaker by analysing the fault current distribution probabilistically when the fault point of specificed line varies. The efficiency of the algorithm was verified by applying the proposed method to IEEE-6bus system and IEEE-30bus system, and probabilistic fault analysing method is verified economic in facility investment by deciding the proper capacity of circuit breaker.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.623-626
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• 2000

The purpose of this paper is to find an efficient solution for multiple constant multiplication (MCM) problem. Since the circuit structure can be represented as a directed acyclic graph, evolutionary computing is considered as an effective tool for optimization of circuit synthesis. In this paper, we propose a stack type operator as a chromosome element to synthesize a directed acyclic graph efficiently. This type of chromosome can represent a graph structure with a set of simple symbols and so we can employ the similar method to a conventional GA.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.769-772
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• 2005

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier(PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance(Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of $0.19mm^2$.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.5
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• pp.777-784
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• 2023

A sense amplifier is an essential peripheral circuit for designing a memory and is used to sense a small differential input signal and amplify it into digital signal. In this paper, a high-speed sense amplifier applicable to in-memory computing circuits is proposed. The proposed circuit reduces sense delay time through transistor Mtail that provides an additional discharge path and improves the circuit performance of the sense amplifier by applying m-GDI (: modified Gate Diffusion Input). Compared with previous structure, the sense delay time was reduced by 16.82%, the PDP(: Power Delay Product) by 17.23%, the EDP(: Energy Delay Product) by 31.1%. The proposed circuit was implemented using TSMC's 65nm CMOS process, while its feasibility was verified through SPECTRE simulation in this study.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.3
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• pp.235-239
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• 1989

A multiplier is proposed for computing multiplication of two arbitrary elements in the finite fields GF($2^m$), and the operation process is described step by step. The modified type of the circuit which is constructed with m-stage feedgack shift register, m-1 flip-flop, m AND gate, and m-input XOR gate is presented by referring to the conventional shift-register multiplier. At the end of mth shift, the shift-register multiplier stores the product of two elements of GF($2^m$); however the proposed circuit in this paper requires m-1 clock times from first input to first output. This circuit is simpler than cellulra-array or systolic multiplier and moreover it is faster than systolic multiplier.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.981-987
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• 1986

This paper describes the CIREX(CIRcuit EXtractor), an automated CMOS circuit extraction program which provides SPICE2 input file by computing circuit connectivity and transistor dimensions from the CIF file. The CIREX also computes parasitic capacitance and resistance which makes it a valuable tool for timing analysis and detailed circuit simulation. A lattice model is used to calculate the interconnection resistances and substrate capacitances which can be replaced, as an option, by a node model for the worst case timing analysis of the circuit.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.291-298
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• 2023

SRAM-based in-memory computing is one of the technologies to solve the bottleneck of von Neumann architecture. In order to achieve SRAM-based in-memory computing, it is essential to design efficient SRAM bit-cell. In this paper, we propose a low-power differential sensing 8+T SRAM bit-cell which reduces power consumption and improves circuit performance. The proposed 8+T SRAM bit-cell is applied to ripple carry adder which performs SRAM read and bitwise operations simultaneously and executes each logic operation in parallel. Compared to the previous work, the designed 8+T SRAM-based ripple carry adder is reduced power consumption by 11.53%, but increased propagation delay time by 6.36%. Also, this adder is reduced power-delay-product (PDP) by 5.90% and increased energy-delay- product (EDP) by 0.08%. The proposed circuit was designed using TSMC 65nm CMOS process, and its feasibility was verified through SPECTRE simulation.