• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.6
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• pp.57-62
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• 2022

Recently, fast storage media such as phage-change memory (PCM) emerge, and memory management policies for slow disk storage need to be revisited. In this paper, we propose a new page replacement policy that makes use of PCM as a swap device of virtual memory systems. The proposed policy aims at reducing write traffic to the swap device as well as reducing the number of page faults pursued by traditional page replacement policies. This is because a write operation in PCM is slow and PCM has limited write endurances. Specifically, the proposed policy focuses on the reduction of page faults when the memory load of the system is high, but it aims at reducing write traffic to storage when free memory space is sufficient. Simulation experiments with various memory reference traces show that the proposed policy reduces write traffic to PCM without performance degradations.

• The Korean Journal of Financial Studies
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• v.2 no.2
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• pp.133-169
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• 1995

• Journal of the Korea Society of Computer and Information
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• v.22 no.12
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• pp.9-15
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• 2017

This paper presents an efficient FTL for NAND flash based SSDs. Address translation information of page mapping based FTLs is stored on flash memory pages and address translation cache keeps frequently accessed entries. The proposed FTL of this paper reduces response time by considering both of temporal and spacial localities of page access patterns in translation cache management. The localities of several well-known traces are evaluated and determine the structure of the cache for high hit ratio. A simulation with several well-known traces shows that the presented FTL reduces response time in comparison to previous FTLs and can be used with relatively small size of caches.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.15-18
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• 2003

Flash memory becomes more important for its fast access speed, low-power, shock resistance and nonvolatile storage. But its native restrictions that have limited 1ifetime, inability of update in place, different size unit of read/write and erase operations need to managed by FTL(Flash Translation Layer). FTL has to control the wear-leveling, address mapping, bad block management of flash memory. In this paper, we focuses on the fast access to address mapping table and proposed the way of faster valid page search in the flash memory using the VPLT(Valid Page Lookup Table). This method is expected to decrease the frequency of access of flash memory that have an significant effect on performance of read and block-transfer operations. For the validations, we implemented the FTL based on Windows CE platform and obtained an improved result.

• International Journal of Internet, Broadcasting and Communication
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• v.14 no.3
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• pp.161-170
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• 2022

Recently, NAND-type flash memory has been regarded to be new promising storage media for large-scale database systems. For flash memory to be employed for that purpose, we need to reduce its expensive update cost caused by the inablity of in-place updates. To remedy such a drawback in flash memory, we propose a new flash-aware buffering scheme that enables virtual flushing of dirty pages. To this end, we slightly alter the tradional algorithms used for the logging scheme and buffer management scheme. By using the mechanism of virtual flushing, our proposed buffering scheme can efficiently prevent the frequenct occureces of page updates in flash storage. Besides the advantage of reduced page updates, the proposed viurtual flushing mechanism works favorably for shorneing a recocery time in the presense of failure. This is because it can reduce the time for redo actions during a recovry process. Owing to those two benefits, we can say that our scheme couble be very profitable when it is incorporated into cutting-edge flash-based database systems.

• IEMEK Journal of Embedded Systems and Applications
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• v.3 no.3
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• pp.158-166
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• 2008

These days, mobile embedded systems adopt flash memory capable of XIP feature since they can reduce memory usage, power consumption, and software load time. XIP provides direct access to ROM and flash memory for processors. However, using XIP incurs unnecessary degradation of applications' performance because direct access to ROM and flash memory shows more delay than that to main memory. In this paper, we propose a memory management framework, dynamic XIP, which can resolve the performance degradation of using XIP. Using a constrained RAM cache, dynamic XIP can dynamically change XIP region according to page access pattern to reduce performance degradation in execution time or energy consumption resulting from native XIP problem. The proposed framework consists of a page profiler gathering applications' memory access pattern using PMU and an XIP manager deciding that a page is accessed whether in main memory or in flash memory. The proposed framework is implemented and evaluated in Linux kernel. Our evaluation shows that our framework can reduce execution time at most 25% and energy consumption at most 22% compared with using XIP-only case adopted in general mobile embedded systems. Moreover, the evaluation shows that in execution time and energy consumption, our modified LRU algorithm with code page filters can reduce more than at most 90% and 80% respectively compared with applying just existing LRU algorithm to dynamic XIP.

• Journal of the Korea Society of Computer and Information
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• v.24 no.11
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• pp.1-9
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• 2019

In this paper, we propose a Small Active Command scheme which reduces the power consumption of the command bus to DRAM. To do this, we target the ACTIVE command, which consists of multiple packets, containing the row address that occupies the largest size among the addresses delivered to the DRAM. The proposed scheme identifies frequently referenced row addresses as Hot pages first, and delivers index numbers of small caches (tables) located in the memory controller and DRAM. I-ACTIVE and I-PRECHARGE commands using unused bits of existing DRAM commands are added for index number transfer and cache synchronization management. Experimental results show that the proposed method reduces the command bus power consumption by 20% and 8.1% on average in the close-page and open-page policies, respectively.

• Journal of Internet Computing and Services
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• v.17 no.5
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• pp.121-129
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• 2016

Company A, an embedded system manufacturer, has been managing multiple development projects. Executives need to understand the risk level of every project and prioritize resource distribution. Traditional project monitoring tools or excel sheets are too complex for calculating the risk factors across a functional organization. Two new charts, "Spear-head Chart" and "Float Chart" were designed to assist high level decision making processes. Two charts were used for weekly executive meetings in order to monitor project progress and rectify project direction. One page graphical monitoring tools in Company A are good enough for high management decision making. Authors explain the characteristics of two charts and propose its practical implementation in real working environment. Spear-head chart was also implemented as a system.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2005.05a
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• pp.420-424
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• 2005

정보 통신 기술의 발달로 엄청난 양의 정보가 World Wide Web을 통해 저장되고 공유된다. 웹 정보의 양이 커질수록 이의 구조화 노력은 점증될 수밖에 없다. 본 논문의 목적은 웹을 유향그래프로 인식하고, 특히 웹 사이트에 초점을 맞추어 웹의 시작페이지(default page)와 이를 제외한 모든 페이지에 대해 최적구조화를 수행하되, 각 개별 웹 페이지를 하나의 종점(terminal page)으로 정의하고, 시작 페이지로부터 각 페이지로의 최적의 경로를 찾아내면서 전체 site의 비용을 최소화할 수 있는 구조를 탐색하는 것이다. 또한 라그랑지안 릴렉세이션을 적용하여 경로 제약조건의 변화에 대해 효율적인 최적해의 변화를 검증하며, 웹의 구조적분석에 적합한지 여부를 적용하는 것이다. 본 연구에서는 웹에 대해 최적화 모델링을 입안 및 분석하였으며, 실험으로서 입안된 모델을 최적화 툴에 적용하여 최적구조화에 부합되는 결과를 얻을 수 있음을 입증하였다.

• Journal of the Korean Society for information Management
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• v.11 no.2
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• pp.131-164
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• 1994

This study shows the design and implementation of cataloging expert system using pattern recognition techniques. This system attemps to demonstrate the feasibility of cataloging in KORMARC format from title page and copyright page without the intervention of humans. The prototype was implemented as a rule-based system in Turbo C. To demonstrate the function and capability of the system, experimental document-group and control document-group was analyzed. The hit ratio of experimental document-group is 94%. On the other hand, the hit ratio of control document-group is 93%, a little bit lower than the experimental group.