• Journal of electromagnetic engineering and science
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• v.5 no.3
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• pp.140-145
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• 2005

In this paper, an experimental investigation for return loss and a software-based prediction for interference level of single-packaged filtering antenna composed of dielectric waveguide filter and PCB(Printed Circuit Board) slot antenna in transceiver module have been carried out with several different feeding structures in millimeter-wave regime. The implementation and embedding method of the existing air-filled waveguide filters working at millimeter-wave frequency on general PCB substrate have been described. In a view of the implementation of each components, the dielectric waveguide embedded in PCB and LTCC(Low Temparature Co-fired Ceramic) substrates has employed the via fences as a replacement with side walls and common ground plane to prevent energy leakage. The characteristics of several prototypes of filtering antenna embedded in PCB substrate are considered by comparing the wideband and transmission characteristics as a function of bent angle of transmission line connecting two components. In addition, as an essential to the packaging of transceiver module working at millimeter-wave, miniaturization technology maintaining the performances of independent components and the important problems caused by integrating and connecting the different components in different layers are described in this paper.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.21-26
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• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.09a
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• pp.183-192
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• 2001

1- Buildup PCB technology is utilized to a bare chip attach substrate technology for packaging of semiconductor chip 2- Requirement for the substrate design rule is described in SIA International Technology Roadmap for Semiconductor. 3- There are seven fabrication methods of build-up technology. 4- Coating and lamination for resin and photo, and laser for micro via hope processes are available. Below $50\mu\textrm{m}$ in diameter is possible. 5- Fine pitch lines down to $30\mu\textrm{m}$ can be achieved by pattern plating with better electrical property. 6- Dielectric loss reduction is a key material improvement item for next generation build-up technology. 7- High band width up to 512 GB/s is possible with current wiring groundrule.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.269-272
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• 2004

Printed circuit boards (PCB) replaced conventional wiring in most electronic equipment I, reducing the size and weight of electronic equipment while improving reliability, uniformity, precision and performance. PCB is used in all kinds of electronic products because they can be mass-produced with very high circuit density and also enable easier trouble-shooting. This paper presents the analyses of the patent information of Build-up PCB which is seen as the most promising solution, as its substrate supports multi-level packaging, thinner board profiles and smaller pitches.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.09a
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• pp.79-94
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• 2002

Root cause -Thermal expansion coefficient mismatch -Tape warpage -Initial die crack (die roughness) Guideline for failure prevention -Optimized tape/Substrate design for minimizing the warpage -Fine surface of die backside Root cause -Thermal expansion coefficient mismatch - Repetitive bending of a signal trace during TC cycle - Solder mask damage Guideline for failure prevention - Increase of trace width - Don't make signal trace passing the die edge - Proper material selection with thick substrate core Root cause -Thermal expansion coefficient mismatch -Creep deformation of solder joint(shear/normal) -Material degradation Guideline for failure Prevention -Increase of solder ball size -Proper selection of the PCB/Substrate thickness -Optimal design of the ball array -Solder mask opening type : NSMD -In some case, LGA type is better

• Journal of the Microelectronics and Packaging Society
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• v.28 no.1
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• pp.47-54
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• 2021

For the bonding of smaller PCB solder bumps of less than 100 microns, an experiment was performed to make up a tin plating solution and find plating conditions in order to produce a bump pattern through tin electroplating, replacing the previous PCB solder bumps process by microballs. After SR patterning, a Cu seed layer was formed, and then, through DFR patterning, a pattern in which Sn can be selectively plated only within the SR pattern was formed on the PCB substrate. The tin plating solution was made based on methanesulfonic acid, and hydroquinone was used as an antioxidant to prevent oxidation of divalent tin ions. Triton X-100 was used as a surfactant, and gelatin was used as a grain refiner. By measuring the electrochemical polarization curve, the characteristics of organic additives in Triton X-100 and gelatin were compared. It was confirmed that the addition of Triton X-100 suppressed hydrogen generation up to -1 V vs. NHE, whereas gelatin inhibited hydrogen generation up to -0.7 V vs. NHE. As the current density increased, there was a general tendency that the grain size became finer, and it was observed that it became finer when gelatin was added.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.43-55
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• 2003

As the development of If industries and their electronic device manufacturing technology have been accelerated recently, the request for electronic devices with small size, light weight, and high performance has been inducing that electronic package and substrate (PCB) companies have to develop substrates with low cost, high dense I/O, excellent thermal properties and electrical properties. Therefore, world-wide chip makers have been setting their own severe reliability standards and requiring their suppliers to keep specification and to develop green, high frequency and high-performing substrates. Because properties of substrates are dependent mainly on their constituent materials, the application of them showing superior properties is expected to satisfy the customer's requirement. Therefore, substrate companies should ensure the superiority of materials and assure their competitive capability of substrates by analyzing the latest trends of technology and properties of the materials.

• International Journal of Internet, Broadcasting and Communication
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• v.7 no.2
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• pp.161-167
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• 2015

The performance of high power LEDs highly depends on the junction temperature. Operating at high junction temperature causes elevation of the overall thermal resistance which causes degradation of light intensity and lifetime. Thus, appropriate thermal management is critical for LED packaging. The main goal of this research is to improve thermal resistance by optimizing and comparing nano-pore silicon-based thermal substrate to insulated metal substrate and direct bonded copper thermal substrate. The thermal resistance of the packages are evaluated using computation fluid dynamic approach for 1 W single chip LED module.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.4
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• pp.50-60
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• 2023

Ball Grid Array (BGA) is a widely used package type due to its high pin density and good heat dissipation. In BGA, solder balls play an important role in electrically connecting the package to the PCB. Therefore, understanding the inelastic deformation of solder balls under various mechanical loads is essential for the robust design of semiconductor packages. In this study, the geometrical effect on the inelastic deformation and fracture of solder balls were analyzed by finite element analysis. The results showed that fracture occurred in both tilted and hourglass shapes under shear loading, and no fracture occurred in all cases under compressive loading. However, when bending was applied, only the tilted shape failed. When shear and bending loads were combined with compression, the stress triaxiality was maintained at a value less than zero and failure was suppressed. Furthermore, a comparison using the Lagrangian-Green strain tensor of the critical element showed that even under the same loading conditions, there was a significant difference in deformation depending on the shape of the solder ball.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.3
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• pp.1-6
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• 2016

The Internet of Things (IoT) is a new technology paradigm demanding one packaged system of various semiconductor and MEMS devices. Therefore, the development of electronic packaging technology with very high connectivity is essential for successful IoT applications. This paper discusses both fan-out wafer level packaging (FOWLP) and 3D stacking technologies to achieve the integrattion of heterogeneous devices for IoT. FOWLP has great advantages of high I/O density, high integration, and design flexibility, but ultra-fine pitch redistribution layer (RDL) and molding processes still remain as main challenges to resolve. 3D stacking is an emerging technology solving conventional packaging limits such as size, performance, cost, and scalability. Among various 3D stacking sequences wafer level via after bonding method will provide the highest connectivity with low cost. In addition substrates with ultra-thin thickness, ultra-fine pitch line/space, and low cost are required to improve system performance. The key substrate technologies are embedded trace, passive, and active substrates or ultra-thin coreless substrates.