• Journal of the Microelectronics and Packaging Society
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• v.28 no.4
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• pp.31-39
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• 2021

In this paper, warpage analysis that separates PCB for PoP (Package on Package) into unit and substrate using FEM (Finite Element Method), analysis of the effect of layer thickness on warpage, and SN (Signal-to-Noise) ratio by Taguchi method was carried. According to the analysis result, the contribution of the circuit layer on warpage was very high in the unit PCB, and the contribution of the outer layer was particularly high. On the other hand, the substrate PCB had a high influence of the circuit layer on warpage, but it was relatively low compared to the unit PCB, and the influence of the solder resist was rather increased. Therefore, considering the unit PCB and the substrate PCB at the same time, it is desirable to design the PCB for PoP layer-by-layer structure so that the outer and inner circuit layers are thick, the top solder resist is thin, and the thickness of the bottom solder resist is between 5 ㎛ and 25 ㎛.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.65-70
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• 2014

Warpage of top packages to form thin package-on-packages was measured with progress of their process steps such as PCB substrate itself, chip bonding, and epoxy molding. The $100{\mu}m$-thick PCB substrate exhibited a warpage of $136{\sim}214{\mu}m$. The specimen formed by mounting a $40{\mu}m$-thick Si chip to such a PCB using a die attach film exhibited the warpage of $89{\sim}194{\mu}m$, which was similar to that of the PCB itself. On the other hand, the specimen fabricated by flip chip bonding of a $40{\mu}m$-thick chip to such a PCB possessed the warpage of $-199{\sim}691{\mu}m$, which was significantly different from the warpage of the PCB. After epoxy molding, the specimens processed by die attach bonding and flip chip bonding exhibited warpages of $-79{\sim}202{\mu}m$ and $-117{\sim}159{\mu}m$, respectively.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.02a
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• pp.1-14
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• 2006

[ $\blacklozenge$ ] PCB에 있어서 Embedded passive 는chip을 직접 내장하는 방법과 특별한 특성을 갖는 재료 및 공법을 사용하여 chip 응 대치하는 방법이 있다. $\blacklozenge$ Embedded passive PCB가 적용될 수 있는 유력한 적용 분야는 소형화가가 요구되는 분야와 고속 특성이 요구되는 분야를 들 수 있고, 따라서, Module, SOP/SIP, Package substrate 등이 우선적으로 적용될 수 있는 분야다. $\blacklozenge$ Embedded capacitor를 적용한 경우, 일반적인 chip capacitor를 적용한 경우보다 더 좋은 전기적인 특성(SRF, Q)을 얻을 수 있으며, solder joint 등의 영향을 포함하면 더욱 좋은 특성이 얻어질 수 있다. $\blacklozenge$ Embedded passive 의 상용화를 위해서, 공차를 관리하는 방법의 개발과 공차에 대한 합리적인 규격을 설정하는 것이 우선 과제이다. $\blacklozenge$ Embedded resistor 의 경우, Laser trim을 적용하여 ${\pm}\;5\%$ 또는 그 이하의 공차를 실현할 수 있고, $30\;K\Omega/sq$. 의 고저항의 적용까지 가능하다. $\blacklozenge$ 고속 신호에서의 noise 감소, module, SIP/SOP 의 소형화를 실현하는데 Embedded passive(혹은 active)PCB 가 기여 할 수 있을 것이고, 이를 위하여 Set 업체, PCB 업체, 재료 업체간의 지속적인 협조가 필요할 것이다.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.2 s.43
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• pp.41-47
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• 2007

Today lots of investigations on Embedded Passive Technology using materials and chip components have been carried out. We fabricated diplexers with 1005 sized-passives, which were made by burying chips in PCB substrate and surface mounting chip on PCB. 6 passive chips (inductors and capacitors) were used for the frequency divisions of $880\;MHz{\sim}960\;MHz(GSM)$ and $1.71\;GHz{\sim}1.88\;GHz(DCS)$. Two types of diplxer were characterized with Network analyzer. The chip buried diplexer showed extra 5db loss and a little deviation of 0.6GHz at aimed frequency areas, whereas the chip mounted diplexer showed man. 0.86dB loss within GSM field and max. 0.68dB within DCS field respectively. But few degradations were observed after $260^{\circ}C$ for 80min baking and $280^{\circ}C$ for 10sec solder floating.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1301-1302
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• 2006

In this paper, embedded spiral inductors are investigated into the PCB substrate for low cost RF SOP applications. The spiral inductors designed with geometrical variations were simulated, fabricated, measured, and characterized by using 3D EM simulator, 8 layered PCB standard process and HP 8510B network analyzer (or verifying their applicability. The fabricated embedded spiral inductor has inductance of 9.4 nH at 800MHz, maximum quality factor of 64.8 at 1.09GHz and self resonant frequency of 3.93GHz, respectively. As the measured inductances and quality factors are well matched with simulated ones. PCB embedded spiral inductors are promising for advanced electronic systems with various functionality, low cost, small size and volume.

• Journal of the Korea Safety Management & Science
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• v.15 no.1
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• pp.109-120
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• 2013

As information-oriented industry has been developed and electronic devices has come to be smaller, lighter, multifunctional, and high speed, the components used to the devices need to be much high density and should have find pattern due to high integration. Also, diverse reliability problems happen as user environment is getting harsher. For this reasons, establishing and securing products and components reliability comes to key factor in company's competitiveness. It makes accelerated test important to check product reliability in fast way. Out of fine pattern failure modes, failure of Electrochemical Migration(ECM) is kind of degradation of insulation resistance by electro-chemical reaction, which it comes to be accelerated by biased voltage in high temperature and high humidity environment. In this thesis, the accelerated life test for failure caused by ECM on fine pattern substrate, $20/20{\mu}m$ pattern width/space applied by Semi Additive Process, was performed, and through this test, the investigation of failure mechanism and the life-time prediction evaluation under actual user environment was implemented. The result of accelerated test has been compared and estimated with life distribution and life stress relatively by using Minitab software and its acceleration rate was also tested. Through estimated weibull distribution, B10 life has been estimated under 95% confidence level of failure data happened in each test conditions. And the life in actual usage environment has been predicted by using generalized Eyring model considering temperature and humidity by developing Arrhenius reaction rate theory, and acceleration factors by test conditions have been calculated.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.7-12
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• 2002

In the measurement of the RF properties, the LTCC substrate must be considered as a system including various conductor patterning processes. In this paper, the LTCC substrate system is compared with a conventional PCB(Printed Circuit Board) substrate such as FR-4, Duroid and Teflon, etc. The microstrip resonator method is employed for the measurement of the RF properties in the range of DC to 20 GHz. Experimental results show that the ring resonator method is suitable for system loss measurement, and the series gap resonator method for dielectric constant measurement. The process of conductor patterning and its effect on the system loss were also studied.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.67-73
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• 2020

In this paper, we used FEM technique to perform warpage and von Mises stress analysis on PCB according to the cavity structures of embedded PCB for FCCSP and the types of prepreg material. One-half substrate model and static analysis are applied to the FEM. According to the analysis results of the warpage, as the gap between the cavity and the chip increased, warpage increased and warpage increased when prepreg material with higher modularity and thermal expansion coefficient was applied. The analysis results of the von Mises stress show that the effect of the gap between the cavity and the chip varies depending on prepreg material. In other words, when material whose coefficient of thermal expansion is significantly higher than that of core material, the stress increased as the gap between the cavity and the chip increased. When the prepreg with the coefficient of thermal expansion lower than the core material is applied, the result of stress is opposite. These results indicate that from a reliability perspective, there is a correlation between the structure of the cavity where embedded chips are loaded and prepreg material.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.25-32
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• 2012

Package for artificial satellite is to produce mass production for high package with reliability certification as well as develop SDRAM (synchronous dynamic RAM) module which has such as miniaturization, mass storage, and high reliability in space environment. It requires sophisticated technology with chip stacking or package stacking in order to increase up to 4Gbits or more for mass storage with space technology. To make it better, we should secure suitable processes by doing design, manufacture, and debugging. Pin type PCB substrate was then applied to QFP-Pin type 3D memory package fabrication. These results show that the 3D memory package for artificial satellite scheme is a promising candidate for the realization of our own domestic technologies.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.45-54
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• 2020

Recently, market demands of miniaturization, high interconnection density, and fine pitch of PCBs continuously keep increasing. Therefore, SLP (substrate like PCB) technology using a modified semi additive process (MSAP) has attracted great attention. In particular, SLP technology is essential for the development of high-capacity batteries and 5G technology for smartphones. In this study, the reliability of the microvia of hybrid SLP, which is made of conventional HDI (high density interconnect) and MSAP technologies, was investigated by experimental and numerical analysis. Through thermal cycling reliability test using IST (interconnect stress test) and finite element numerical analysis, the effects of various parameters such as prepreg properties, thickness, number of layers, microvia size, and misalignment on microvia reliability were investigated for optimal design of SLP. As thermal expansion coefficient (CTE) of prepreg decreased, the reliability of microvia increased. The thinner the prepreg thickness, the higher the reliability. Increasing the size of the microvia hole and the pad will alleviate stress and improve reliability. On the other hand, as the number of prepreg layers increased, the reliability of microvia decreased. Also, the larger the misalignment, the lower the reliability. In particular, among these parameters, CTE of prepreg material has the greatest impact on the microvia reliability. The results of numerical stress analysis were in good agreement with the experimental results. As the stress of the microvia decreased, the reliability of the microvia increased. These experimental and numerical results will provide a useful guideline for design and fabrication of SLP substrate.