• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.5
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• pp.889-895
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• 2008

In this paper a Fractional-N frequency synthesizer is designed for UHF RFID readers. It satisfies the ISO/IEC frequency band($860{\sim}960MHz$) and is also applicable to mobile RFID readers. A VCO is designed to operate at 1.8GHz band such that the LO pulling effect is minimized. The 900MHz differential I/Q LO signals are obtained by dividing the differential signal from an integrated 1.8GHz VCO. It is designed using a $0.18{\mu}m$ RF CMOS process. The measured results show that the designed circuit has a phase noise of -103dBc/Hz at 100KHz offset and consumes 9mA from a 1.8V supply. The channel switching time of $10{\mu}s$ over 5MHz transition have been achieved, and the chip size including PADs is $1.8{\times}0.99mm^2$.

• Journal of the Korea Institute of Military Science and Technology
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• v.3 no.2
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• pp.131-139
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• 2000

A design of CPS attitude determination system is described in this paper. The designed system is a low cost high precision 24 channel single frequency GPS(Global Positioning System) receiver which provides a precise absolute heading and pitch (or roll) as well as a position. It uses commercial chip-set and consists of two RF parts, two signal-tracking parts, a processor, memory parts and I/Os. In order to determine precise attitude, accurate carrier phase measurements and an efficient integer ambiguity resolution method are required. To meet these requirements, a PLL (Phase Locked Loops) is designed, and an algorithm called ARCE (Ambiguity Resolution with Constraint Equation) is adopted. The hardware and software structure of the system will be described, and the performance evaluated under various conditions will be presented. The test results will promise that more reliable navigation system be possible because the system provides all navigational information such as position, velocity, time and attitude.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.54-56
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• 2005

The paper proposes the solar photovoltaic power generation system method for photovoltaic system to solve the power shortage due the sudden power demand. So that supplied electric power to system at appearance during surplus electric power minute and unit moment link driving with common use system is available, digital PLL circuit system voltage through composition and phase of solar photovoltatic power generation system to do synchronization do. Feed forward controller was applied to get fast current response Solar cell that is changed by solar radiation always kept the maximum output when it used Step up chopper. The dynamic character had checked through simulation used Matlab Sumulink and confirmed through an experiment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.929-935
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• 2003

An analog/digital mixed mode ASIC for network synchronization of ATM switching system has been designed and fabricated. This ASIC generates a 234.7/46.94 ㎒ system clock and 77.76/19.44 ㎒ user clock using 46.94 ㎒ transmitted clocks from other systems. It also includes digital circuits for checking and selecting of the transmitted clocks. For effective ASIC design, full custom technique is used in 2 analog PLL circuits design, and standard cell based technique is used in digital circuit design. Resistors and capacitors for analog circuits are specially designed which can be fabricated in general CMOS technology, so the chip can be implemented in 0.8$\mu\textrm{m}$ digital CMOS technology with no expensive. Testing results show stable 234.7 ㎒ and 19.44 ㎒ clocks generation with each 4㎰ and 17㎰ of low ms jitter.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.860-866
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• 2016

An injection-locked ring phase-locked loop (ILRPLL) using a charge-stored complementary switch (CSCS) injection technique is described in this paper. The ILRPLL exhibits a wider lock range compared to other conventional ILRPLLs, owing to the improvement of the injection effect by the proposed CSCS. A frequency calibration loop and a device mismatch calibration loop force the frequency error to be zero to minimize jitter and reference spur. The prototype chip fabricated in 65-nm CMOS technology achieves a $285-fs_{rms}$ integrated jitter at GHz from the reference clock of 52 MHz while consuming 7.16 mW. The figure-of-merit of the ILRPLL is -242.4 dB.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.359-369
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• 2020

In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.4
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• pp.25-31
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• 2017

This paper presents a 270/540/750/1500-Mb/s serial-data transmitter realized in a $0.13-{\mu}m$ CMOS technology for the applications of video data transmission. A low-cost RG-58 copper cable(5C-HFBT-RG6T) is exploited as a transmission medium connected to a single BNC connector, which shows cable loss 45 dB in maximum at 1.5 GHz. RLGC modeling provides an equivalent circuit for SPICE simulations of which characteristics are very similar to the measured cable loss. The loss can be compensated by pre-emphasis at transmitter and equalization at receiver if needed. Measurements of the proposed transmitter chip demonstrate the operations of 270-Mb/s, 540-Mb/s, 750-Mb/s and 1.5-Gb/s, and provide the output voltage levels of $370mV_{pp}$ at 1.5 Gb/s even with the pre-emphasis turned-off. The total power consumption is 104 mW from 1.2/3.3-V supplies and the chip occupies the area of $1.65{\times}0.9mm^2$.

• ETRI Journal
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• v.36 no.3
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• pp.352-360
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• 2014

This paper presents a 900 MHz zero-IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ${\Delta}{\Sigma}$ fractional-N frequency synthesizer. In the RF front end, re-use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current-driven passive mixer in Rx and voltage-mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty-cycle in local oscillator clocks. The overall Rx-baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a $0.18{\mu}$ CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of -2 dBm, a sensitivity level of -103 dBm at 100 Kbps with PER < 1%, an Rx input $P_{1dB}$ of -11 dBm, and an Rx input IP3 of -2.3 dBm.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.498-498
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• 2013

Atmospheric Pressure Plasmas have pioneered a new field of plasma for biomedical application bridging plasma physics and biology. Biological and medical applications of plasmas have attracted considerable attention due to promising applications in medicine such as electro-surgery, dentistry, skin care and sterilization of heat-sensitive medical instruments [1]. Traditional approaches using electronic devices have limits in heating, high voltage shock, and high current shock for patients. It is a great demand for plasma medical industrial acceptance that the plasma generation device should be compact, inexpensive, and safe for patients. Microwave-excited micro-plasma has the highest feasibility compared with other types of plasma sources since it has the advantages of low power, low voltage, safety from high-voltage shock, electromagnetic compatibility, and long lifetime due to the low energy of striking ions [2]. Recent experiment [2] shows three-log reduction within 180-s treatment of S. mutans with a low-power palm-size microwave power module for biomedical application. Experiments using microwave plasma are discussed. This low-power palm-size microwave power module board includes a power amplifier (PA) chip, a phase locked loop (PLL) chip, and an impedance matching network. As it has been a success, more compact-size module is needed for the portability of microwave devices and for the various medical applications of microwave plasma source. For the plasma generator, a 1.35-GHz coaxial transmission line resonator (CTLR) [3] is used. The way of reducing the size and enhancing the performances of the module is examined.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.51-56
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• 2010

In this paper, a novel Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF. The size of chip is $255{\mu}m$ $\times$ $935.5{\mu}m$ including the LF. The proposed P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.