• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.57-58
• /
• 2005

The properties such as capacitance and resonant frequency are important in embedded capacitors. Accurate equivalent model is required to find these properties of embedded capacitor. In this paper, we investigate to analyze the properties of high-K embedded capacitor which was fabricated by Low Temperature Co-fired Ceramic (LTCC). Modeling based on partial element equivalent circuit (PEEC) method is performed using HSPICE circuit simulation. This modeling methodology can provide the good inspection of embedded capacitor to device engineer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.06a
• /
• pp.38-39
• /
• 2006

In this paper, we describe a method of accurate modeling capacitor in Low Temperature Co-fired Ceramic(LTCC). We obtain building blocks that present characterization of test structure through partial element equivalent circuit (PEEC) method. The extracted model of building blocks can be used for predicting behaviors of capacitors with different geometries. This method can provide the good inspection of capacitor to device engineer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.5
• /
• pp.404-408
• /
• 2003

The characterization for several multi-layer embedded inductors with different structures was investigated. The optimized equivalent circuit models for several test structures were obtained from HSPICE. Building blocks are modeled using Partial element equivalent circuit method. The mean and the standard deviation of model parameters were extracted and predictive modeling was performed on different test structure. From this study, the characteristic of multi-layer inductors can be predicted.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.3
• /
• pp.49-60
• /
• 2002

A systematic design approach for Power distribution network (PDN) is presented aiming at applications to DRAM module designs. Three main stages are comprised in this design approach: modeling and simulation of a PDN based on a two-dimensional transmission line structure employing a partial element equivalent circuit (PEEC); verification of the simulation results through comparison to measured values; and design space scanning with PDN parameters. Impedance characteristics for do-coupling capacitors are analyzed to devise an effective way to stabilize power and ground plane Performance within a target level of disturbances. Self-impedance and transfer-impedance are studied in terms of distance between circuit features and the size of do-coupling capacitors. A simple equation has been derived to find the do-coupling capacitance values yielding impedance lower than design target, and thereby reducing the overall computation time. The effectiveness of the design methodology has been demonstrated using a DRAM module with discrete do-coupling capacitors and a strip structure.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.9
• /
• pp.259-269
• /
• 2012

With the lower supply voltage and the higher operating frequency in integrated circuits, the analysis of the power distribution network (PDN) including on-chip inductances becomes more important. In this paper, an effective inductance extraction method for a regular on-chip power grid structure is proposed. The loop inductance model applicable to chip layout is proposed and the inductance extraction tool using the proposed inductance model based on post layout RC circuits is developed. The accuracy of the proposed loop model and the developed tool is verified by comparing the test circuit simulation results with those from the partial element equivalent circuit (PEEC) model. The voltage fluctuation from the RLC circuits extracted by the developed tool was examined for the analysis of on-chip inductance effects. The significance of on-chip power grid inductance was investigated by the co-simulation of chip-package-PCB.

• Journal of the Microelectronics and Packaging Society
• /
• v.13 no.4
• /
• pp.9-15
• /
• 2006

This paper shows the impedance profile of PEEC(Partial Equivalent Electrical Circuit) PDN(Power Distribution Networks) including core and I/O circuit. Through the simulated results, we find that the core power noise having connection with I/O power is affected by I/O switching. Also, using designed $74{\times}5inch$ DLL(Delay Locked Loop) test board, we analyzed the effect of power noise on operation region of chip. Jitter of a DLL measure for frequency of $50{\sim}400MHz$ and compared with impedance obtained result of simulation. Jitter of a DLL are increased near about frequency of 100MHz. It is reason that the resonant peak of PDNs has an impedance of more the 1ohm on 100MHz. we present the impedance profile of a chip and board for the decoupling capacitor reduced the target impedance. Therefore, power supply network design should be considered not only decoupling capacitors but also core switching current and I/O switching current.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07b
• /
• pp.678-681
• /
• 2002

In this paper, Characterization for several 3-D embedded passive elements with different structures was performed. The equivalent circuit optimization for embedded inductor was performed by HSPICE simulation software. After extracting each parameter values, the difference of parameter from each structure was examined. From this work, effective characterization of passive devices with similar structure will be possible.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.07b
• /
• pp.607-610
• /
• 2003

The characteristic prediction and analysis of 3-dimensional (3-D) solenoid-type embedded inductors is investigated. The four different structures of 3-D inductor are fabricated by using low-temperature cofired ceramic (LTCC) process. The circuit model parameters of the each building block are optimized and extracted using the partial element equivalent circuit method and HSPICE circuit simulator. Based on the model parameters, predictive modeling is applied for the structures composed of the combination of the modeled building blocks. And the characteristics of test structures, such as self-resonant frequency, inductance and Q-factor, are analyzed. This approach can provide the characteristic conception of 3-D solenoid embedded inductors for structural variations.

• Journal of Power Electronics
• /
• v.9 no.2
• /
• pp.308-319
• /
• 2009

An increasing number of power electronic applications require high power density. Therefore, the switching frequency and switching speed have to be raised considerably. However, the very fast switching transients induce a strong voltage and current ringing. In this work, a novel damping concept is introduced where the parasitic wiring inductances are advantageously magnetically coupled with a damping layer for attenuating these unwanted oscillations. The proposed damping layer can be implemented using standard materials and printed circuit board manufacturing processes. The system behavior is analyzed in detail and design guidelines for a damping layer with optimized RC termination network are given. The effectiveness of the introduced layer is determined by layout parasitics which are calculated by application of the Partial Element Equivalent Circuit (PEEC) simulation method. Finally, simulations and measurements on a laboratory prototype demonstrate the good performance of the proposed damping approach.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.14 no.12
• /
• pp.1276-1282
• /
• 2003

The SMT(Surface Mount Type) ferrite bead used to reduce the influx of power bus noise is modeled with parallel capacitor(C), series resistor(R) and series inductor(L). The simple equivalent circuit modeling doesn't agree with the measurement result. In this paper, we proposed the accurate equivalent circuit model of the ferrite bead at wide frequency range(50 MHz∼3 GHz) and analyzed the noise effect to the high speed IC(Integrate Circuit) with ferrite bead or not.