• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.05a
• /
• pp.259-262
• /
• 2012

The most of military systems that developed today are composed with many sub-systems for mission execution. The test of military systems for delivery test of mass product such that part test, PCB test, component test, integration test. This paper discusses improving productivity test method that functional test of PCB has a various function. Improving productivity is minimize testing item by man and minimize kind of tester, so that decrease product cost by production time for test. PCB tester be developed many kind of test method that systems were developed by many different engineers. This paper study testing check point for testing that how to minimize of kind of tester, how to automatic test for all of function that have inputs and outputs.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.12
• /
• pp.2808-2814
• /
• 2012

The most of military systems that developed today are composed with many sub-systems for mission execution. The test of military systems for delivery test of mass product such that part test, PCB test, component test, integration test. Improving productivity is minimize testing item by man and minimize kind of tester, so that decrease product cost by production time for test. PCB tester be developed many kind of test method that systems were developed by many different engineers. This article studies testing check point for testing that how to minimize of kind of tester, how to automatic test for all of function that have inputs and outputs. Development of tester for improving productivity requires classify functional allocation of main system and sub system, sub system require PCB for functional allocation start on preliminary design period for reducing testing item and testing fixture.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.46 no.2
• /
• pp.22-27
• /
• 2009

In this paper, an automatic functional inspection system EVT (Emulated Vision Tester) for LCD drive module PCB has been proposed and implemented. Typical automatic inspection system such as probing methods and vision-based systems are widely known and used, however, there exist undetectable defects due to critical timing factors which they may miss to catch from LCD equipments. Especially typical vision-based systems have inconsistency on acquisition of images so that distinction between gray scales can be difficult which results in low level of performance and reliability on the inspection results. The proposed EVT system is pure hardware solution. It directly compares pattern signals from a pattern generator to output signals from LCD drive module. It also inspects variety of analog signals such as voltage, resistance, wave forms and so forth. The EVT system not only shows high performance in terms of reliability and processing speed but reduces costs on inspection and maintenance. Also, full automation of entire production line can be realized when EVT is applied in in-line inspection processes.

• Proceedings of the KIEE Conference
• /
• 2008.10b
• /
• pp.211-212
• /
• 2008

본 논문에서는 LCD 구동 모들 PCB의 기능 검사를 위한 자동 검사시스템인 EVT(Emulated Vision Tester)를 제안하고 구현하였다. 기존의 대표적인 자동검사 방법으로는 전기적 검사나 영상기반 검사방식이 있으나 전기적 검사만으로는 Timing이 주요한 변수가 되는 LED 장비에서는 검출할 수 없는 구동불량이 존재하며 영상기반 검사는 영상획득에 일관성이 결여되거나 Gray Scale의 구분이 불명확하며 검출결과의 재현성이 떨어진다. EVT 시스템은 Pattern Generator에서 인가된 입력 패턴 신호라 구동모듈을 통한 후 출력되는 디지털 신호를 직접 비교하여 패턴을 검사하고 아날로그 신호 (전압, 저항, 파형)의 이상 여부도 신속 정확하게 검사할 수 있는 H/W적인 방법이다. 높은 검출 신뢰도와 빠른 처리 속도 뿐만 아니라 간결한 시스템 구성으로 원가절감 실현 등 많은 장점을 가진다.

• Proceedings of the KIEE Conference
• /
• 2002.11c
• /
• pp.601-604
• /
• 2002

In this paper, the timing do-skew modeling for a high speed logic tester channels is developed. The time delay of each channel in a logic tester are different from other channels and it can produce timing error in a test. To get the best timing accuracy in the test with a logic tester, the timing skew must be compensated. The timing skew of channels is due to the difference of time delay of pin-electronics devices composing channels and length of metal line placed on PCB. The expected timing difference of channels can be calculated according to the specifications of pin electronics devices and strip line modeling of PCB. With the calculated delay time, the timing skew compensation circuit has been designed. With the timing skew compensation circuit, the timing calibration of a logic tester can be peformed easily and automatically without other time measuring instruments. The calibration method can then be directly applied to logic testers in mass production lines.

• IE interfaces
• /
• v.23 no.1
• /
• pp.58-67
• /
• 2010

The purpose of this paper is to present the development processes of the assembly line tester of power transmission for lift truck. Because power transmission is most important part of lift truck, all assembled powertrain parts must be inspected for operational defects, pressures and RPM. Developed assembly line tester is designed to take about 25 minutes for inspecting each assembled power transmission and located it at the end of assembled line. The assembly line no-load tester consists of three parts: (1) the driving hardware part; for installing and operating the transmission. (2) control PCB part; send data from sensors to a computer and control driving part, (3) operation software of no-load tester; for an automatic inspection or manual inspection, for database management and printing transcripts.

• Journal of the KSME
• /
• v.34 no.2
• /
• pp.112-117
• /
• 1994

최근의 전자기기는 반도체 기술의 급속한 발전에 따라 소형화, 고기능화 및 다양화 뿐만 아니라 경박단소화되는 추세에 있다. 이러한 시장의 요구에 대응하여 표면실장용 전자부품이 등장하여 그 사용이 점차증가하고 있고 여기에 발맞춰 국내 . 외 전자기기 제조업체가 제품내의 PCB를 SMD화하는 추세에 있다. 따라서 표면실장 부품의 조립을 위한 고밀도, 고정도의 실장기술의 개발이 요구되고 있다. 또한 부품 자동삽입 등 기존의 방법들로 조립된, 전자기기 내부에 사용 되는 PCB의 조립상태 및 각 부품의 특성들을 검사하기 위한 In-circuit Tester의 기술도 빠른 속도로 발전하여 자동화되어가고 있는 추세에 있다. 이에 따라 본 연구소에서는 '90년에 능 Mounter GCA-M2000 모델을 개발 완료하였고 현재 관련 사업부에서 양산중에 있으며, 아날로그 방식 및 디지털 방식의 In-circuit Tester 모델도 개발 완료하여 현재 양산 중에 있다. 이 지면을 빌어 소개할 기회를 갖고자 한다.

• Proceedings of the KIEE Conference
• /
• 1988.07a
• /
• pp.269-272
• /
• 1988

This paper deals with the test strategy on the short-open for the printed circuit board. A group testing algorithm, which is the several testing point to be measured redefined as one of the testing points, was suggested. As a result, the total testing time was reduced to 30${\sim}$50 percent.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2002.11a
• /
• pp.21-26
• /
• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• Korean Journal of Materials Research
• /
• v.18 no.3
• /
• pp.117-122
• /
• 2008

Micro-sized bumps on a multi-layered build-up PCB were fabricated by pulse-reverse copper electroplating. The values of the current density and brightener content for the electroplating were optimized for suitable performance with maximum efficiency. The micro-bumps thus electroplated were characterized using a range of analytical tools that included an optical microscope, a scanning electron microscope, an atomic force microscope and a hydraulic bulge tester. The optical microscope and scanning electron microscope analyses results showed that the uniformity of the electroplating was viable in the current density range of $2-4\;A/dm^2$; however, the uniformity was slightly degraded as the current density increased. To study the effect of the brightener concentration, the concentration was varied from zero to 1.2 ml/L. The optimum concentration for micro-bump electroplating was found to be 0.6 ml/L based on an examination of the electroplating properties, including the roughness, yield strength and grain size.