• Journal of the Korean Ceramic Society
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• v.34 no.7
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• pp.699-702
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• 1997

The cross sectional image of thin oxide failure of MOS device could be observed by Emission Microscope and Focused Ion Beam at the weak point. The oxide failures in low electric field was associated with the presence of a particle or abnormal pattern. The failures occuring at medium field are related to a pit of Si substrate. The pits could be originated from the microdefects of Cz Si wafer.

• Tribology and Lubricants
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• v.18 no.4
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• pp.260-266
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• 2002

In this study, the effects of oxide layer farmed on the wear tracks of TiN coated silicon wafer on friction and wear characteristics were investigated. Silicon wafer was used for the substrate of coated disk specimens, which were prepared by depositing TiN coating with 1 ${\mu}{\textrm}{m}$ in coating thickness. AISI 52100 steel ball was used fur the counterpart. The tests were performed both in air for forming oxide layer on the wear track and in nitrogen to avoid oxidation. This paper reports characterization of the oxide layer effects on friction and wear characteristics using X-ray diffraction(XRD), Auger electron spectroscopy(AES), scanning electron microscopy (SEM) and multi-mode atomic force microscope(AFM).

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.10b
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• pp.167-168
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• 2002

In this study, the effects of oxide layer formed on the wear tracks of TiN coated silicon wafer on friction characteristics were investigated. Silicon wafer was used for the substrate of coated disk specimens, which were prepared by depositing TiN coating with $1\;{\mu}m$ in coating thickness. AISI 52100 steel balls were used for the counterpart. The tests were performed both in air for forming oxide layer on the wear track and in nitrogen to avoid oxidation. This paper reports characterization of the oxide layer effects on friction characteristics using X-ray diffraction (XRD). scanning electron microscopy (SEM) and friction force microscope (FFM).

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.451-457
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• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.

• Journal of Welding and Joining
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• v.19 no.3
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• pp.305-310
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• 2001

UBM-coated Si-wafer was fluxlessly soldered with glass substrate in $N_2$ atmosphere using plasma cleaning method. The bulk Sn-37wt.%Pb solder was rolled to the sheet of $100\mu\textrm{m}$ thickness in order to bond a solder disk by fluxless 1st reflow process. The oxide layer on the solder surface was analysed by AES(Auger Electron Spectroscopy). Through rolling, the oxide layer on the solder surface became thin, and it was possible to bond a solder disk on the Si-wafer with fluxless process in $N_2$ gas. The Si-wafer with a solder disk was plasma-cleaned in order to remove oxide layer formed during 1st reflow and soldered to glass by 2nd reflow process without flux in $N_2$ atmosphere. The thickness of oxide layer decreased with increasing plasma power and cleaning time. The optimum plasma cleaning condition for soldering was 500W 12min. The joint was sound and the thicknesses of intermetallic compounds were less than $1\mu\textrm{m}$.

• Journal of the Semiconductor & Display Technology
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• v.2 no.2
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• pp.9-15
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• 2003

This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12" silicon wafer for spin etcher. Halogen lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and adaptive filtering. Test wafers with three kinds of priori-known films, polysilicon(300 nm), silicon-oxide(500 nm) and silicon-oxide(600 nm), are measured while the wafer is spinning at 20 Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 0.8% error.rror.

• Korean Journal of Materials Research
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• v.32 no.9
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• pp.396-402
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• 2022

In this study, surface roughness and interfacial defect characteristics were analyzed after forming a high-k oxide film on the surface of a prime wafer and a test wafer, to study the possibility of improving the quality of the test wafer. As a result of checking the roughness, the deviation in the test after raising the oxide film was 0.1 nm, which was twice as large as that of the Prime. As a result of current-voltage analysis, Prime after PMA was 1.07 × 10 A/cm² and Test was 5.61 × 10 A/cm², which was about 5 times lower than Prime. As a result of analyzing the defects inside the oxide film using the capacitance-voltage characteristic, before PMA Prime showed a higher electrical defect of 0.85 × 10¹² cm^-2 in slow state density and 0.41 × 10¹³ cm^-2 in fixed oxide charge. However, after PMA, it was confirmed that Prime had a lower defect of 4.79 × 10¹¹ cm^-2 in slow state density and 1.33 × 10¹² cm^-2 in fixed oxide charge. The above results confirm the difference in surface roughness and defects between the Test and Prime wafer.

• Journal of the Korean institute of surface engineering
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• v.51 no.3
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• pp.185-190
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• 2018

Dopant-free silicon heterojunction solar cells using Transition Metal Oxide(TMO) such as Molybdenum Oxide($MoO_X$) and Vanadium Oxide($V_2O_X$) have been focused on to increase the work function of TMO in order to maximize the work function difference between TMO and n-Si for a high-efficiency solar cell. One another way to increase the work function difference is to control the silicon wafer resistivity. In this paper, dopant-free silicon heterojunction solar cells were fabricated using the wafer with the various resistivity and analyzed to understand the effect of n-Si work function. As a result, it is shown that the high passivation and junction quality when $V_2O_X$ deposited on the wafer with low work function compared to the high work function wafer, inducing the increase of higher collection probability, especially at long wavelength region. the solar cell efficiency of 15.28% was measured in low work function wafer, which is 34% higher value than the high work function solar cells.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.3
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• pp.134-142
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• 1995

We discovered that each distinct shape of the roof-shaped peaks of (111) facets, which are generated on (110) cross-section of the directly bonded (100) silicon wafer pairs after KOH etching, can be mapped to one of three conditions of the interfacial oxide existing at the bonding interface as follows. That is, thick solid line can be mapped to stabilization, thin solid line to disintegration, and thin broken line to spheroidization. also we confirmed that most of the interfacial oxides of a well-aligned wafer pairs were disintegrated and spheroidized through high-temperature annealing process above 900$^{\circ}$C while the oxide was stabilized persistently when two wafers are bonded rotationally around their common axis perpendicular to the wafer planes.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.81-85
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• 2013

Wafer stacking technology becomes more important for the next generation IC technology. It requires new process development such as TSV, wafer bonding, and wafer thinning and also needs to resolve wafer warpage, power delivery, and thermo-mechanical reliability for high volume manufacturing. In this study, Cu CMP which is the key process for wafer bonding has been studied using Cu CMP and oxide CMP processes. Wafer samples were fabricated on 8" Si wafer using a damascene process. Cu dishing after Cu CMP and oxide CMP was $180{\AA}$ in average and the total height from wafer surface to bump surface was approximately $2000{\AA}$.