• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 추계학술대회 논문집
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• pp.129-132
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• 1998

In this paper, we have studied the effect of electron reflection on shadow mask on which tungsten oxide film is coated and have studied the variation of beam mislanding with coating thickness in CRT. We found the method to be able to control coating thicknessed and optimum coating thickness of tungsten oxide film was 1∼2$\mu\textrm{m}$. Mislanding of electron beam was reduced about 20∼48% with increasing coating thickness in CRT

• 대한전자공학회논문지
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• 제27권1호
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• pp.91-95
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• 1990

We study the process for the reduction of bird's beak at LOCOS processing with changing the representative coefficients, oxide thickness, silicon nitride thickness, oxidetion temperature and field oxide thickness that induced the condition of bird'beak. In order to eliminate the gate oxide defects induced by selective oxidation, we used additional sacrific oxidatio. Finally we obtained the length of bird's beak to be 5000\ulcornerby SEM.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.388-388
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• 2010

Molybdenum oxide thin films were deposited on p-type Si(100) by an RF magnetron sputtering method. The physical and chemical properties of these films were studied with X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS) techniques. The thickness of molybdenum oxide thin films was measured by spectroscopic ellipsometer (SE) and the thickness was about 200 nm. As the oxygen gas pressure increased, the thickness was decreased, the phases of the thin films were changed, and the amount of metallic Mo decreased but the contents of $Mo^{6+}$ species increases.

• 전기전자학회논문지
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• 제24권1호
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• pp.194-199
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• 2020

본 논문에서는 비대칭 무접합 이중게이트 MOSFET에 대한 문턱전압이동을 상단과 하단 게이트 산화막 두께에 따라 분석하였다. 비대칭 구조에서는 상단과 하단 게이트 산화막 두께를 달리 제작할 수 있으므로 문턱전압이동을 일정하게 유지하면서 상단 게이트에서 발생할 수 있는 누설전류를 감소시키기 위하여 상단과 하단 산화막 두께를 조정할 수 있다. 이를 위하여 해석학적 문턱전압 모델을 제시하였으며 이 모델은 2차원 시뮬레이션 값과 잘 일치하였다. 결과적으로 일정한 문턱전압이동을 유지하면서 하단 게이트 산화막 두께를 감소시키면 상단 게이트 산화막 두께를 증가시킬 수 있어 상단 게이트에서 발생할 수 있는 누설전류를 감소시킬 수 있을 것이다. 특히 하단 게이트 산화막 두께가 증가하여도 문턱전압이동에는 큰 영향을 미치지 않는다는 것을 관찰하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.100-106
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• 2010

The impact of surface quantization on device parameters of a Si metal oxide semiconductor (MOS) capacitor has been analyzed in the present work. Variation of conduction band bending, position of discrete energy states, variation of surface potential, and the variation of inversion carrier concentration at charge centroid have been analyzed for different gate voltages, substrate doping concentrations and oxide thicknesses. Oxide thickness calculated from the experimental C-V data of a MOS capacitor is different from the actual oxide thickness, since such data include the effect of surface quantization. A correction factor has been developed considering the effect of charge centroid in presence of surface quantization at strong inversion and it has been observed that the correction due to surface quantization is crucial for highly doped substrate with thinner gate oxide.

• 한국표면공학회지
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• 제34권1호
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• pp.17-24
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• 2001

A model for quantifying the effect of steam pressure on the oxide thickness growth was developed based on the experimental data available. First, empirical equations for the thickness estimation of oxide formed in 1 atm steam were made. The oxide growth kinetics turned out to be dependent on 0.4th power of oxidation time. With an assumption that the transition oxide thickness be only a function of temperature, a model for the enhancement of steam pressure on oxide growth was developed. The enhancement coefficient for steam pressure is calculated to be 0.01~0.013 $bar^{-}$. The developed model generally well explains the experimental data.a.

• 한국정보통신학회논문지
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• 제20권3호
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• pp.571-576
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• 2016

비대칭 이중게이트 MOSFET는 다른 상하단 게이트 산화막 두께를 갖는다. 상하단 게이트 산화막 두께 비에 대한 문턱전압이하 스윙 및 전도중심의 변화에 대하여 분석하고자한다. 문턱전압이하 스윙은 전도중심에 따라 변화하며 전도중심은 상하단의 산화막 두께에 따라 변화한다. 비대칭 이중게이트 MOSFET는 문턱전압이하 스윙의 저하 등 단채널효과를 감소시키기에 유용한 소자로 알려져 있다. 포아송방정식의 해석학적 해를 이용하여 문턱전압이하 스윙을 유도하였으며 상하단의 산화막 두께 비가 전도중심 및 문턱전압이하 스윙에 미치는 영향을 분석하였다. 문턱전압이하 스윙 및 전도중심은 상하단 게이트 산화막 두께 비에 따라 큰 변화를 나타냈다. 특히 하단 게이트 전압은 문턱전압이하 스윙에 큰 영향을 미치며 하단게이트 전압이 0.7V 일 때 $0<t_{ox2}/t_{ox1}<5$의 범위에서 문턱전압이하 스윙이 약 200 mV/dec 정도 변화하는 것을 알 수 있었다.

• 전자공학회논문지A
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• 제32A권7호
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• pp.58-68
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• 1995

Polysilicon capacitors with pyrogenic oxide and TEOX oxide as insulators were fabricated to develop capacitors which can be applied to analog CMOS IC, and the characteristics of the capacitors were compared with each other. The morphology of bottom polysilicon in pyrogenic oxide capacitor is degraded due to the generaged protuberances of the polysilicon grain during oxidataion. The polysilican capacitor with pyrogenic oxide of 57 nm thickness showed that the effective potential barrier height of 0.45 eV is much less than that of MOS capacitor (3.2 eV)when the top electrode is biased with a positive volgate. The morphology of the polysilicon capacitor with TEOS oxide, however, was not degraded during oxide deposition by LPCVD. The polysilicon capacitor with TEOS oxide of 54 nm thickness showed the effective potential barrier height of 1.28 eV when the top electrode is biased with a negative voltage. Therefore, it is concluded that the polysilicon capacitor with TEOS oxide is more applicable to analog CMOS IC than the pyrogenic oxide polysilicon capacitor.

• E2M - 전기 전자와 첨단 소재
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• 제8권6호
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• pp.727-736
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• 1995

This paper examines the characteristics and physical properties of the scaled MONOS nonvolatile memory device for low programming voltage EEPROM. The capacitor-type MONOS memory devices with the nitride thicknesses ranging from 41.angs. to 600.angs. have been fabricated. As a result, the 5V-programmable MONOS device has been obtained with a 20ms programming time by scaling the nitride thickness to 57.angs. with a tunneling oxide thickness of 19.angs. and a blocking oxide thickness of 20.angs.. Measurement results of the quasi-static C-V curves indicate, after 10$\^$6/ write/erase cycles, that the devices are degraded due to the increase of the silicon-tunneling oxide interface traps. The 10-year retention is impossible for the device with a nitride less than 129.angs.. However, the MONOS memory device with 10-year retentivity has been obtained by increasing the blocking oxide thickness to 47.angs.. Also, the memory traps such as the nitride bulk trap and the blocking oxide-nitride interface trap have been investigated by measuring the maximum flatband voltage shift and analyzing through the best fitting method.

• 한국표면공학회지
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• 제30권3호
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• pp.191-201
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• 1997

Non-passivated electrolytic tinplates withour conventinal chemical treatment self-oxidize in ambient atmosphere to from yellow stain on the outermost surface during the long-term storage. The degree of yellowness of the stain increased linerly with the oxide thickness due to the interfeefence color of the $SnO_2$ Even though the thickness of the oxide layer was very thin, less than 100$\AA$ , it exerts an undesirable influence on the can-making processes, particularly the stripping behavior after ironing. Investigations were carried out on the morphologies of the coating layer, the changes in oxide thickness during successive can-making processes and the averge friction coefficients with the different oxide thinkness. These oxide layers were broken up and distributed within the bulk tin coating during the ironing process. This redistribution of the oxide layer prvented smooth pressing-aside of the tin coating layer, resulting in an increase in the ironing friction coefficient. As the friction was increased, the residual stress along the can wall thinkness(i.e., the hoop stress) was also increased. Due to both the oxibe layer accumulation, which increased the friction coefficient, and the hoop stress, can stripping efficiency without roll-back is reduced.