• 전자공학회논문지A
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• 제29A권8호
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• pp.56-62
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• 1992

This paper is analyzed the charge trapping and electrical properties of 0(Oxide), NO(Nitrided oxide) and ONO(Reoxidized nitrided oxide) as dielectric films in MIS structures. We have processed bottom oxide and top oxide by the thermal method, and nitride(Si$_{3}N_{4}$) by the LPCVD(Low Pressure Chemical Vapor Deposition) method on P-type(100) Silicon wafer. We have studied the charge trapping properties of the dielectrics by using a computer controlled DLTS system. All of the dielectric films are shown peak nearly at 300K. Those are bulk traps. Many trap densities which is detected in NO films, but traps. Many trap densities which is detected in NO films. Varing the nitride thickness, the trap densities of thinner nitride is decreased than the thicker nitride. Finally we have found that trap densities of ONO films is affected by nitride thickness.

• 한국표면공학회지
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• 제53권5호
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• pp.249-256
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• 2020

As the size of manufacturing equipment for LCD and OLED displays increases, replacement of existing heavy stainless steel components with light metals, such as aluminum alloys, is being more important in semiconducting and display manufacturing industries. To use aluminum alloys for components in semiconducting and display industries, it is important to develop a new anodization method for improved performance of anodic oxide films than conventional anodization method based on sulfuric acid. In this work, optimum applied current density and the best sealing methods for anodic oxide films in 3% oxalic acid were explored. Experimental results showed 2.5 A/dm2 is the best applied current density for improved hardness and dielectric breakdown voltage. Sealing of the anodic oxide films further improved their hardness, dielectric breakdown voltage and resistance to HCl, by which application of anodic oxide films become applicable for components in semiconducting and display industries.

• 한국표면공학회지
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• 제33권4호
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• pp.217-221
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• 2000

The gate oxide thickness is becoming thinner and thinner in order to speed up the semiconductor CMOS devices. We have investigated very thin$ SiO_2$ gate oxide layers and found anomaly between the thickness determined with capacitance measurement and these obtained with cross-sectional high resolution transmission electron microscopy. The thicknesses difference of the two becomes important for the thickness of the oxide below 5nm. We propose that the variation of dielectric constant in thin oxide films cause the anomaly. We modeled the behavior as (equation omitted) and determined $\varepsilon_{bulk}$=3.9 and $\varepsilon_{int}$=-4.0. We predict that optimum $SiO_2$ gate oxide thickness may be $20\AA$ due to negative contribution of the interface dielectric constant. These new results have very important implication for designing the CMOS devices.s.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.318.1-318.1
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• 2016

Hafnium Oxide (HfOx) has been attracted as a promising gate dielectric for replacing SiO2 in gate stack applications. In this paper, Metal-Oxide-Semiconductor (MOS) capacitor with solution processed HfO2 high-k material as a dielectric were fabricated. The solvent using $HfOCl2{\cdot}8H2O$ dissolve in 2-Methoxy ethanol was prepared at 0.3M. The HfOx layers were deposited on p-type silicon substrate by spin-coating at $250^{\circ}C$ for 5 minutes on a hot plate and repeated the same cycle for 5 times, followed by annealing process at 350, 450 and $550^{\circ}C$ for 2 hours. When the annealing temperature was increased from 350 to $550^{\circ}C$, capacitance value was increased from 337 to 367 pF. That was resulted from the higher temperature of HfOx which have more crystallization phase, therefore dielectric constant (k) was increased from 11 to 12. It leads to the formation of dense HfOx film and improve the ability of the insulator layer. We confirm that HfOx layer have a good performance for dielectric layer in MOS capacitors.

• 한국표면공학회지
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• 제57권1호
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• pp.8-13
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• 2024

Anodizing of Al6061 alloy was conducted in two different electrolytes of 20% sulfuric acid and 8% sulfuric acid + 3 % oxalic acid solutions at a constant current or decreasing current density conditions, and its dielectric breakdown voltage was measured. The surface morphology of anodic oxide films was observed by TEM and thermal treatment was carried out at 400 ℃ for 2 h to evaluate the resistance of the anodic oxide films to crack initiation. The anodic oxide film formed in 8% sulfuric acid + 3 % oxalic acid solution showed higher dielectric breakdown voltage and better resistance to crack initiation at 400 ℃ than that formed in 20% sulfuric acid solution. The dielectric breakdown voltage increased 6 ~12% by applying decreasing current density comparing with a constant current density.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.799-802
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• 2002

For purer images in plasma display panel, a new dielectric compositions containing neodymium oxide were studied. In the present study, Pb-based compositions were used as mother glasses (PbO-$B_2O_3-SiO_2Nd_2O_3$) and thermal, dielectric, and optical properties were measured. As a result the new dielectric with a rare-earth oxide made selectively visible light penetrated and showed especially noticeable absorption properties at 585 nm that is surely related to the erroneous gas from Ne discharge. Thus, this light purple colored glass composition will help PDP to come true to get better imaging process.

• 전자공학회논문지D
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• 제34D권6호
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• pp.43-49
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• 1997

Tungsten poycide has studied gate oxide reliability and dielectric strength charactristics as the composition of gate electrode which applied submicron on CMOS and MOS device for optimizing gate electrode resistivity. The gate oxide reliability has been tested using the TDDB(time dependent dielectric breakdwon) and SCTDDB (stepped current TDDB) and corelation between polysilicon and WSi$_{2}$ layer. iN the case of high intrinsic reliability and good breakdown chracteristics on polysilicon, confirmed that tungsten polycide layer is a better reliabilify properities than polysilicon layer. Also, hole trap is detected on the polysilicon structure meanwhile electron trap is detected on polycide structure. In the case of electron trap, the WSi$_{2}$ layer is larger interface trap genration than polysilicon on large POCL$_{3}$ doping time and high POCL$_{3}$ doping temperature condition. WSi$_{2}$ layer's leakage current is less than 1 order and dielectric strength is a larger than 2MV/cm.

• Journal of Industrial and Engineering Chemistry
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• 제67권
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• pp.478-485
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• 2018

The effect of reduced graphene oxide (RGO) addition on the dielectric and piezoelectric behavior of the polyvinylidene fluoride (PVDF) films was studied. Dielectric constant increased by four times and piezoelectric coefficient also increased twice by the addition of RGO in the PVDF films. Based on capacitance-voltage and ellipsometry measurements and the Kramers-Kronig transformation, it is concluded that the enhanced dielectric and piezoelectric properties of the PVDF/RGO films resulted from the increased orientational polarization due to a phase transition from nonpolar crystalline ${\alpha}$ phase to polar crystalline ${\beta}$ phase in the PVDF structure.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.37-40
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• 1999

For the first time, charge trapping nonvolatile semiconductor memories with the deoxidized oxynitride gate dielectric is proposed and demonstrated. Gate dielectric wit thickness of less than 1 nm have been grown by postnitridation of pregrown thermal silicon oxides in NO ambient and then reoxidation. The nitrogen distribution and chemical state due to NO anneal/reoxidation were investigated by M-SIMS, TOF-SIMS, AES depth profiles. When the NO anneal oxynitride film was reoxidized on the nitride film, the nitrogen at initial oxide interface not only moved toward initial oxide interface, but also diffused through the newly formed tunnel oxide by exchange for oxygen. The results of reoxidized oxynitride(ONO) film analysis exhibits that it is made up of SiO$_2$(blocking oxide)/N-rich SiON interface/Si-rich SiON(nitrogen diffused tunnel oxide)/Si substrate. In addition, the SiON and the S1$_2$NO Phase is distributed mainly near the tunnel oxide, and SiN phase is distributed mainly at tunnel oxide/Si substrate interface.

• Transactions on Electrical and Electronic Materials
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• 제17권6호
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• pp.380-382
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• 2016

The mechanism for instability under PBS (positive bias stress) in amorphous SIZO (Si-In-Zn-O) thin-film transistors was investigated by analyzing the charge trapping mechanism. It was found that the bulk traps in the SIZO channel layer and the channel/dielectric interfacial traps are not created during the PBS duration. This result suggests that charge trapping in gate dielectric, and/or in oxide semiconductor bulk, and/or at the channel/dielectric interface is a more dominant mechanism than the creation of defects in the SIZO-TFTs.