• Journal of Power Electronics
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• v.15 no.4
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• pp.1131-1138
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• 2015

This study presents an input-powered high-efficiency interface circuit for energy harvesting systems, and introduces a zero standby power design to reduce power consumption significantly while removing the external power supply. This interface circuit is composed of two stages. The first stage voltage doubler uses a positive feedback control loop to improve considerably the conversion speed and efficiency, and boost the output voltage. The second stage active diode adopts a common-grid operational amplifier (op-amp) to remove the influence of offset voltage in the traditional comparator, which eliminates leakage current and broadens bandwidth with low power consumption. The system supplies itself with the harvested energy, which enables it to enter the zero standby mode near the zero crossing points of the input current. Thereafter, high system efficiency and stability are achieved, which saves power consumption. The validity and feasibility of this design is verified by the simulation results based on the 65 nm CMOS process. The minimum input voltage is down to 0.3 V, the maximum voltage efficiency is 99.6% with a DC output current of 75.6 μA, the maximum power efficiency is 98.2% with a DC output current of 40.4 μA, and the maximum output power is 60.48 μW. The power loss of the entire interface circuit is only 18.65 μW, among which, the op-amp consumes only 2.65 μW.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.8
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• pp.551-556
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• 2000

A zero-voltage-switching(ZVS) programmable power supply employing the ZVS active clamp forward converter is suggested. Through the analysis on operation region of the supply, the constant power region and the maximum current limit region are clearly identified. Furthermore, the duty ratio range corresponding to the variation range of the output voltages and the control scheme at the minimum duty ration region are presented. Finally, in order to vefity the validity of the operation for the proposed power supply, experimental evaluation results obtained on an 1kW prototype power supply for the 198~242VAC input voltage range(220VAC$\pm$10%), the 0~25V output voltage range, and the 100kHz switching frequency are presented.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.10
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• pp.581-586
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• 2002

To improve the current waveform of diode rectifiers, we propose a new operating principle for the voltage-doubler diode rectifiers. In the conventional voltage-doubler rectifier circuit, relatively large capacitors are used to boost the output voltage, while the proposed circuit uses smaller ones and a small reactor not to boost the output voltage but improve the input current waveform. A circuit design method is shown by experimentation and confirmed simulation. The experimental results of the proposed diode rectifier satisfies the harmonic guide lines. A high input power factor of 97(%) and an efficiency of 98[%] are also obtained. The new rectifier with no controlled switches meet the harmonic guide lines, resulting in a simple, reliable and low-cost at-to dc converters in comparison with the boost-type current-improving circuits. This paper proposes a nonlinear impedance circuit composed by diodes and inductors or capacitors. This circuit needs no control circuits and switches, and the impedance value is changed by the polarity of current or voltage. And this paper presents one of these applications to improve the input current of capacitor input diode rectifiers. The rectifier using the nonlinear impedance circuit is constructed with four diodes and four capacitors in addition to the conventional rectifiers, that is, it has eight diodes and five capacitors, including a DC link capacitor. It makes harmonic components of the input current reduction and the power factor improvement. Half pulse-width modulated (HPWM) inverter was explained compared with conventional pulse width modulated(PWM) inverter. Proposed HPWM inverter eliminated dead-time by lowering switching loss and holding over-shooting.

• Journal of Power Electronics
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• v.12 no.3
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• pp.377-386
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• 2012

An interleaved bridgeless buck-boost AC/DC converter is presented in this paper to achieve the characteristics of low conduction loss, a high power factor and low harmonic and ripple currents. There are only two power semiconductors in the line current path instead of the three power semiconductors in a conventional boost AC/DC converter. A buck-boost converter operated in the boundary conduction mode (BCM) is adopted to control the active switches to achieve the following characteristics: no diode reverse recovery problem, zero current switching (ZCS) turn-off of the rectifier diodes, ZCS turn-on of the power switches, and a low DC bus voltage to reduce the voltage stress of the MOSFETs in the second DC/DC converter. Interleaved pulse-width modulation (PWM) is used to control the switches such that the input and output ripple currents are reduced such that the output capacitance can be reduced. The voltage doubler topology is adopted to double the output voltage in order to extend the useable energy of the capacitor when the line voltage is off. The circuit configuration, principle operation, system analysis, and a design example are discussed and presented in detail. Finally, experiments on a 500W prototype are provided to demonstrate the performance of the proposed converter.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.3
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• pp.224-230
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• 2016

In this study, a single-power-conversion series-resonant ac-dc converter with high efficiency and high power factor is proposed. The proposed ac-dc converter consists of single-ended primary-inductor converter with an active-clamp circuit and a voltage doubler with series-resonant circuit. The active-clamp circuit clamps the surge voltage and provides zero-voltage switching of the main switch. The series-resonant circuit consists of leakage inductance $L_{lk}$ of the transformer and resonant capacitors $ C_{r1}$ and $ C_{r2}$. This circuit also provides zero-current switching of output diodes $D_1$ and $D_2$. Thus, the switching loss of switches and reverse-recovery loss of output diodes are considerably reduced. The proposed ac-dc converter also achieves high power factor using the proposed control algorithm without the addition of a power factor correction circuit and a dc-link electrolytic capacitor. A detailed theoretical analysis and the experimental results for a 1kW prototype are discussed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.7
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• pp.771-777
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• 2008

In this paper, a frequency doubler using modified time-delay technique is proposed. A voltage controlled delay line (VCDL) in the proposed frequency doubler compensates the group delay time mismatching between input and delayed signal. With the group delay time matching and waveform shaping using the adjustable Schmitt triggers, the unwanted fundamental component($f_0$) and the higher order harmonics such as third and fourth are diminished excellently. In result, only the doubled frequency component($2f_0$) appears dominantly at the output port. The frequency doubler is designed at 1.15 GHz of $f_0$ and fabricated with TSMC $0.18\;{\mu}m$ CMOS process. The measured output power at $2f_0$ is 2.67 dBm when the input power is 0 dBm. The obtained suppression ratio of $f_0,\;3f_0$, and $4f_0$ to $2f_0$ are 43.65, 38.65 and 35.59 dB, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.10
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• pp.109-117
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• 2004

In this paper, a K-band local oscillator composed of a VCDRO(Voltage Controlled Dielectric Resonator Oscillator), GaAs MESFET, and Reflector type frequency doubler has been designed and fabricated. TO obtain a good phase noise performance of a VCDRO, a active device was selected with a low noise figure and a low flicker noise MESFET and a dielectric resonator was used for selecting stable and high oscillation frequency. Especially, to have a higher conversion gain than a conventional doubler as well as a good harmonic suppression performance with circuit size reduced a doubler structure was employed as the Reflector type composed of a reflector and a open stub of quarter wave length for rejecting the unwanted harmonics. The measured results of fabricated oscillator show that the output power was 5.8 dBm at center frequency 12.05 GHz and harmonic suppression -37.98 dBc, Phase noise -114 dBc at 100 KHz offset frequency, respectively, and measured results show of fabricated frequency doubler, the output power at 5.8 dBm of input power is 1.755 dBm conversion gain 1.482 dB, harmonic suppression -33.09 dBc, phase noise -98.23 dBc at 100 KHz offset frequency, respectively. This oscillator could be available to a local oscillator in K-band which used frequency doubler techniques.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.1
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• pp.23-30
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• 2014

This paper proposes a single power-conversion ac-dc converter with a dc-link capacitor-less and high power factor. The proposed converter is derived by integrating a full-bridge diode rectifier and a series-resonant active-clamp dc-dc converter. To obtain a high power factor without a power factor correction circuit, this paper proposes a suitable control algorithm for the proposed converter. The proposed converter provides single power-conversion by using the proposed control algorithm for both power factor correction and output control. Also, the active-clamp circuit clamps the surge voltage of switches and recycles the energy stored in the leakage inductance of the transformer. Moreover, it provides zero-voltage turn-on switching of the switches. Also, a series-resonant circuit of the output-voltage doubler removes the reverse-recovery problem of the output diodes. The proposed converter provides maximum power factor of 0.995 and maximum efficiency of 95.1% at the full-load. The operation principle of the converter is analyzed and verified. Experimental results for a 400W ac-dc converter at a constant switching frequency of 50kHz are obtained to show the performance of the proposed converter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.93-100
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• 2009

This paper presents a step up four channel DC-DC converter using charge pump voltage doubler structure. Our goal is to design and implement DC-DC converter for capacitive SP4T RF MEMS switch in front end module in wireless transceiver system. Charge pump structure is small and consume low power 3.3V input voltage is boosted by DC-DC Converter to $11.3{\pm}0.1V$, $12.4{\pm}0.1V$, $14.1{\pm}0.2V$ output voltage With 10MHz switching frequency. By using voltage level shifter structure, output of DC-DC converter is selected by 3.3V four channel selection signals and transferred to capacitive MEMS devices. External passive devices are not used for driving DC-DC converter. The total chip area is $2.8{\times}2.1mm^2$ including pads and the power consumption is 7.52mW, 7.82mW, 8.61mW.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.4
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• pp.315-322
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• 2009

In the conventional boost converter, the actual duty cycle is limited as the output voltage increases due to increased voltage and current stress of the switch and diode and voltage surge caused by diode reverse recovery. In this paper a new non-isolated boost converter suitable for high gain applications is proposed. The proposed converter has voltage gain of around 6 when the duty cycle is 0.5. Since ZVS is achieved under CCM, the proposed converter has wide ZVS range. Also, voltage ratings of switch and diode are the same as one third of output voltage, and ratings of input and output passive components are reduced due to the interleaving. In addition voltage surge caused by diode reverse recovery is negligible due to ZCS turn-off of diodes. Operating principle of the proposed converter is described and validated through theoretical analysis, simulation and experiment.