• Composites Research
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• v.36 no.5
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• pp.349-354
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• 2023

Poly(3-hexylthiophene) (P3HT) is a conjugated polymer that is highly soluble in organic solvents and is readily available. However, its electrical properties as an active channel in electronic devices are not enough for practical applications, necessitating further improvement in the properties. In this study, we demonstrate that the blending of two P3HT polymers (i.e., regio-regular (RR) P3HT and regio-random (RRa) P3HT) with different regioregularities can significantly improve charge transport characteristics of the blend films. The morphological and electrical properties of the blend films were systematically investigated by varying the ratio between two P3HT polymers. Atomic force microscopy (AFM), X-ray diffraction (XRD), and UV-visible absorption spectroscopy (UV-vis) were employed to evaluate the morphological and optoelectronic properties of the blend films. The crystallinity of the blend films increased with increasing the content of RRa-P3HT to 20 wt% and gradually decreased as the content increased to 80%. Consistently, the highest charge carrier mobility was obtained from the blend films containing 20 wt% RRa-P3HT, which value was measured to be 0.029 cm²/V·s. The values gradually decreased to 0.0007 cm²/V·s with increasing the content of RRa-P3HT to 80 wt%.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.400-401
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• 2012

그래핀(Graphene)은 열 전도도가 높고 전자 이동도(200 000 cm2V-1s-1)가 우수한 전기적 특성을 가지고 있어 전계 효과 트랜지스터(Field effect transistor; FET), 유기 전자 소자(Organic electronic device)와 광전자 소자(Optoelectronic device) 같은 반도체 소자에 응용 가능하다. 그러나 에너지 밴드 갭이 없기 때문에 소자의 전기적 특성이 제한되는 단점이 있다. 최근에는 아크 방출(Arc discharge method), 화학적 기상 증착법(Chemical vapor deposition; CVD), 이온-조사법(Ion-irradiation) 등을 이용한 이종원자(Hetero atom)도핑과 화학적 처리를 이용한 기능화(Functionalization) 등의 방법으로 그래핀을 도핑 후 에너지 밴드 갭을 형성시키는 연구 결과들이 보고된 바 있다. 그러나 이러한 방법들은 표면이 균일하지 않고, 그래핀에 많은 결함들이 발생한다는 단점이 있다. 이러한 단점을 극복하기 위해 자가조립 단층막(Self-assembled monolayers; SAMs)을 이용하여 이산화규소(Silicon oxide; SiO2) 기판을 기능화한 후 그 위에 그래핀을 전사하면 그래핀의 일함수를 쉽게 조절하여 소자의 전기적 특성을 최적화할 수 있다. SAMs는 그래핀과 SiO2 사이에 부착된 매우 얇고 안정적인 층으로 사용된 물질의 특성에 따라 운반자 농도나 도핑 유형, 디락 점(Dirac point)으로부터의 페르미 에너지 준위(Fermi energy level)를 조절할 수 있다[1-3]. 본 연구에서는 SAMs한 기판을 이용하여 그래핀의 도핑 효과를 확인하였다. CVD를 이용하여 균일한 그래핀을 합성하였고, 기판을 3-Aminopropyltriethoxysilane (APTES)와 Borane-Ammonia(Borazane)을 이용하여 각각 아민 기(Amine group; -NH2)와 보론 나이트라이드(Boron Nitride; BN)로 기능화한 후, 그 위에 합성한 그래핀을 전사하였다. 기판 위에 NH2와 BN이 SAMs 형태로 존재하는 것을 접촉각 측정(Contact angle measurement)을 통해 확인하였고, 그 결과 NH2와 BN에 의해 그래핀에 도핑 효과가 나타난 것을 라만 분광법(Raman spectroscopy)과 X-선 광전자 분광법(X-ray photoelectron spectroscopy: XPS)을 이용하여 확인하였다. 본 연구 결과는 안정적이면서 패턴이 가능하기 때문에 그래핀을 기반으로 하는 반도체 소자에 적용 가능할 것이라 예상된다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.7-11
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• 2011

In this paper, we proposed a simple and high-yield printing process for source and drain electrodes of organic thin film transistor (OTFT). The surface energy of PVP (poly 4-vinylphenol) gate dielectric was decreased from 56 $mJ/m^2$ to 45 $mJ/m^2$ by adding fluoride of 3000ppm into it. Meanwhile the surface energy of source and drain (S/D) electrodes area on the PVP was increased to 87 $mJ/m^2$ by treating the areas, which was patterned by photolithography, with oxygen plasma, maximizing the surface energy difference from the other areas. A conductive polymer, G-PEDOT:PSS, was deposited on the S/D electrode areas by brushing painting process. With such a simple process we could obtain a high yield of above 90 % in $16{\times}16$ arrays of OTFTs. The performance of OTFTs with the fluoride-added PVP was similar to that of OTFTs with the ordinary PVP without fluoride, generating the mobility of 0.1 $cm^2/V.sec$, which was sufficient enough to drive electrophoretic display (EPD) sheet. The EPD panel employing the OTFT-backpane successfully demonstrated to display some patterns on it.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.363-363
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• 2014

Ruthenium (Ru) has attractive material properties due to its promising characteristics such as a low resistivity ($7.1{\mu}{\Omega}{\cdot}cm$ in the bulk), a high work function of 4.7 eV, and feasibility for the dry etch process. These properties make Ru films appropriate for various applications in the state-of-art semiconductor device technologies. Thus, it has been widely investigated as an electrode for capacitor in the dynamic random access memory (DRAM), a metal gate for metal-oxide semiconductor field effect transistor (MOSFET), and a seed layer for Cu metallization. Due to the continuous shrinkage of microelectronic devices, better deposition processes for Ru thin films are critically required with excellent step coverages in high aspect ratio (AR) structures. In these respects, atomic layer deposition (ALD) is a viable solution for preparing Ru thin films because it enables atomic-scale control of the film thickness with excellent conformality. A recent investigation reported that the nucleation of ALD-Ru film was enhanced considerably by using a zero-valent metallorganic precursor, compared to the utilization of precursors with higher metal valences. In this study, we will present our research results on the synthesis and characterization of novel ruthenium complexes. The ruthenium compounds were easy synthesized by the reaction of ruthenium halide with appropriate organic ligands in protic solvent, and characterized by NMR, elemental analysis and thermogravimetric analysis. The molecular structures of the complexes were studied by single crystal diffraction. ALD of Ru film was demonstrated using the new Ru metallorganic precursor and O2 as the Ru source and reactant, respectively, at the deposition temperatures of $300-350^{\circ}C$. Self-limited reaction behavior was observed as increasing Ru precursor and O2 pulse time, suggesting that newly developed Ru precursor is applicable for ALD process. Detailed discussions on the chemical and structural properties of Ru thin films as well as its growth behavior using new Ru precursor will be also presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.7-13
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• 2008

This paper proposes a newly structured circuit that can compensate current deviation of a data driver circuit for OLED. A conventional data drivel circuit for OLED cannot compensate the current deviation at the data drivel circuit output terminal generated by MOS process change, but the proposed data drivel circuit can authorize uniform value of current to an OLED panel by calibrating the current deviation at the output terminal. The proposed circuit can minimize current deviation of the output current via process change by connecting the circuit for data output current with a common interconnect line through addition of a switching transistor to the existing data output circuit. The circuit proposed in this paper has been designed based on an OLED panel supporting $128{\times}128$ resolution, and the process used for driver circuit development is 0.35um. As a result of the experiment in this study, the output current of the data driver circuit proposed here has 1% range of error, while 9% range of severe changes was demonstrated in the case of the previous data driver circuit. When using the data driver circuit for OLED proposed in this paper, high definition OLED display can be actualized and the circuit can be applied to mobile display devices requiring high quality display features.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.77-78
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• 2006

최근 flexible OLED의 구동에 사용하기 위한 유기박막트랜지스터(Organic Thin Film Transistor, OTFT)의 연구에서는 용매에 용해되어 spin coating이 가능한 재료의 개발에 관심을 두고 있다. 현재 pentacene으로는 아직 spin coating으로 제작할 수 있는 상용화된 제품이 없고 spin coating이 가능한 활성층 물질(active material)로 P3HT가 쓰이고 있다. 본 연구에서는 용해 가능한 P3HT 활성층 물질과 여러 종류의 용해 가능한 게이트 절연물(gate insulator, Gl)을 사용하여 안정된 소자를 구현할 수 있는 공정을 개발하는 목적으로 metal-insulator-semironductor(MIS) 소자를 제작하여 C-V 특성을 측정하고 분석하였다. 먼저 7mm${\times}$7mm 크기의 pyrex glass 시편 위에 바닥 전극으로 $1600{\AA}$ Au을 증착하고 spin coating 방식을 이용하여 PVP, PVA, PVK, BCB, Pl의 5종류의 게이트 절연층을 각각 형성하였고 그 위에 같은 방법으로 P3HT를 코팅하였다. P3HT 코팅 시 bake 공정의 유무와 spin rpm의 변화에 따른 P3HT의 두께를 측정하였다. Gl의 종류별로 주파수에 따른 capatltancc를 측정하여 비교, 분석하였다. C-V 측정 결과 PVP, PVA, PVK, BCB, Pl의 단위 면적당 capacitance 값은 각각 1.06, 2.73, 2.94, 3.43, $2.78nF/cm^2$로 측정되었다. Threshold voltage, $V_{th}$는 각각 -0.4, -0.7, -1.6, -0.1, -0.2V를 나타냈다. 주파수에 따른 capacitance 변화율을 측정한 결과 Gl 물질 모두 주파수가 높을수록 capacitance가 점점 감소하는 경향을 보였으나 1${\sim}$2nF 이내의 범위에서 작은 변화율만 나타냈다. P3HT의 두께와 bake 온도를 변화시켜 C-V 값을 측정한 결과 차이는 없었다. FE-SEM으로 관찰한 결과에서도 두께나 온도에 따른 P3HT의 표면 morphology 차이를 확인할 수 없었다. 본 연구에서 PVK와 P3HT의 조합이 수율(yield)면에서 가장 안정적이면서 $3.43\;nF/cm^2$의 가장 높은 capacitance 값을 나타내고 $V_{th}$ 값 또한 -1.6V로 가장 낮은 값을 보였다.