• ETRI Journal
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• v.39 no.3
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• pp.428-436
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• 2017

State-of-the-art processors require increasingly complicated memory services for high performance and low power consumption. In particular, they request transfers within a burst in a wrap-around order to minimize the miss penalty of a cache. However, synchronous dynamic random access memories (SDRAMs) do not always generate transfers in the wrap-round order required by the processors. Thus, a memory subsystem rearranges the SDRAM transfers in the wrap-around order, but the rearrangement process may increase memory latency and waste the bandwidth of on-chip interconnects. In this paper, we present a memory subsystem that is effective for the wrapping bursts of a cache. The proposed memory subsystem makes SDRAMs generate transfers in an intermediate order, where the transfers are rearranged in the wrap-around order with minimal penalties. Then, the transfers are delivered with priority, depending on the program locality in space. Experimental results showed that the proposed memory subsystem minimizes the memory performance loss resulting from wrapping bursts and, thus, improves program execution time.

• The Journal of Korean society of community based occupational therapy
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• v.9 no.2
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• pp.13-22
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• 2019

Objective : The purpose of this technical research is to determine decline of episodic memory by normal aging focucing on object, spatial location, and temporal order memory. Methods : We allocated seventy-seven of healthy adults from twenty to eighty years old, and performed computer-based cognitive tasks which were consisted of the object, spatial location, and temporal order memory. We used OpenSesame(OpenSesame Inc, OR), put ten pictures people normally see in their daily life, and evaluated those aspects through asking the objects types, object spatial locations, and picture temporal orders from 10 sheets of the picture. Results : Object and spatial location memory were not affected by normal aging whereas, temporal order memory significantly decreased with normal aging. Specifically, temporal order memory for in their age of forty was significantly decreased compared with their age of twenty and object memory at their age of eighty was relatively high compared to spatial location and temporal order memory. We found out that temporal order memory worse fastest and object memory lasted longest. Conclusion : In this study, we confirmed characteristics of declines of episodic memory consisting of object, spatial location, and temporal order memory. Notably, we could specifically identify declines of spatial location and temporal order memory with normal aging previous studies investigated on a limited basis using conventional neuropsychological assessments. These findings would be helpful to screen impairment in episodic memory by normal aging and provide an evidence that cognitive intervention for healthy older adults needs to include spatial and temporal aspect of memory.

• Journal of International Academy of Physical Therapy Research
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• v.9 no.4
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• pp.1591-1595
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• 2018

The number of healthy older adults is rapidly increasing recently owing to the increase of the elderly population. Therefore, programs for improving the cognitive functions of these healthy seniors are actively being expanded. This study aimed to prevent the decline of cognitive function due to aging by applying a program enhancing cognitive functions to healthy older adults. The objective of this study was to evaluate the effects of Korean computer-based cognitive rehabilitation program (CoTras), which is commonly used in cognitive therapy for the aging, on the memory of the elderly. The subjects had scored at least 24 points in MMSE-K. CoTras was applied once a week (30 minutes) for one month. Electronic pegboard programs were used as an evaluation tool: order memory (difficulty=low) and location memory (difficulty=medium). The order and location memories were compared before and after the intervention. The Wilcoxon signed rank-sum test was used for the study at the significance level of ${\alpha}=.05$. The results showed that CoTras significantly improved order memory and location memory. Therefore, CoTras can be applied to the healthy elderly for improving that memory improvement training has a positive impact on healthy older adults result in the development of memory enhancement programs can be expanded in the future.

• Journal of Information Processing Systems
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• v.14 no.2
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• pp.499-509
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• 2018

Recently, hybrid transactional memory (HyTM) has gained much interest from researchers because it combines the advantages of hardware transactional memory (HTM) and software transactional memory (STM). To provide the concurrency control of transactions, the existing HyTM-based studies use a bloom filter. However, they fail to overcome the typical false positive errors of a bloom filter. Though the existing studies use a global lock, the efficiency of global lock-based memory allocation is significantly low in multi-core environment. In this paper, we propose an efficient hybrid transactional memory scheme using near-optimal retry computation and sophisticated memory management in order to efficiently process transactions in multi-core environment. First, we propose a near-optimal retry computation algorithm that provides an efficient HTM configuration using machine learning algorithms, according to the characteristic of a given workload. Second, we provide an efficient concurrency control for transactions in different environments by using a sophisticated bloom filter. Third, we propose a memory management scheme being optimized for the CPU cache line, in order to provide a fast transaction processing. Finally, it is shown from our performance evaluation that our HyTM scheme achieves up to 2.5 times better performance by using the Stanford transactional applications for multi-processing (STAMP) benchmarks than the state-of-the-art algorithms.

• Dementia and Neurocognitive Disorders
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• v.22 no.4
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• pp.148-157
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• 2023

Background and Purpose: Episodic memory is a system that receives and stores information about temporally dated episodes and their interrelations. Our study aimed to investigate the relevance of episodic memory to time perception, with a specific focus on simultaneity/order judgment. Methods: Experiment 1 employed the simultaneity judgment task to discern differences in time perception between patients with mild cognitive impairment or dementia, and age-matched normals. A mathematical analysis capable of estimating subjects' time processing was utilized to identify the sensory and decisional components of temporal order and simultaneity judgment. Experiment 2 examined how differences in temporal perception relate to performance in temporal order memory, in which time delays play a critical role. Results: The temporal decision windows for both temporal order and simultaneity judgments exhibited marginal differences between patients with episodic memory impairment, and their healthy counterparts (p = 0.15, t(22) = 1.34). These temporal decision windows may be linked to the temporal separation of events in episodic memory (Pearson's ρ = -0.53, p = 0.05). Conclusions: Based on our findings, the frequency of visual events accumulated and encoded in the working memory system in the patients' and normal group appears to be approximately (5.7 and 11.2) Hz, respectively. According to the internal clock model, a lower frequency of event pulses tends to result in underestimation of event duration, which phenomenon might be linked to the observed time distortions in patients with dementia.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.157-169
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• 2013

Scale Invariant Feature Transform (SIFT) generates image features widely used to match objects in different images. Previous work on hardware-based SIFT implementation requires excessive internal memory and hardware logic [1]. In this paper, a new hardware organization is proposed to implement SIFT with less memory and hardware cost than the previous work. To this end, a parallel Gaussian filter bank is adopted to eliminate the buffers that store intermediate results because parallel operations allow all intermediate results available at the same time. Furthermore, the processing order is changed from the raster-scan order to the block-by-block order so that the line buffer size storing the source image is also reduced. These techniques trade the reduction of memory size with a slight increase of the execution time and external memory bandwidth. As a result, the memory size is reduced by 94.4%. The proposed hardware for SIFT implementation includes the Descriptor generation block, which is omitted in the previous work [1]. The addition of the hardwired descriptor generation improves the computation speed by about 30 times when compared with the previous work.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.5
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• pp.389-394
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• 2004

In this paper, according to characteristics of flash memory, a memory recycling method is proposed in order to decrease the necessary cost preventing performance degradation at the same time, In order to optimize the demanding costs, the new approach partitions the search space of flash memory segments into K segment groups, A method for memory space allocation, in addition, is proposed in order to satisfy the goal of even wearing over the total memory space, The optimized configuration of the proposed method is achieved through experiments, The fact that the newly proposed methods outperform the existing approaches regarding cost and performance is evaluated by simulations, Furthermore the experimental results demonstrate that the memory allocation method affects even wearing in great deal.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.11a
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• pp.52-53
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• 2012

Belief propagation (BP) is a commonly used global energy minimization algorithm for solving stereo matching problem in 3D reconstruction. However, it requires large memory bandwidth and data size. In this paper, we propose a novel memory-efficient algorithm of BP in stereo matching on the Graphics Processing Units (GPU). The data size and transfer bandwidth are significantly reduced by storing only a part of the whole message. In order to maintain the accuracy of the matching result, the local messages are reconstructed using shared memory available in GPU. Experimental result shows that there is almost an order of reduction in the global memory consumption, and 21 to 46% saving in memory bandwidth when compared to the conventional algorithm. The implementation result on a recent GPU shows that we can obtain 22.8 times speedup in execution time compared to the execution on CPU.

• International Journal of Internet, Broadcasting and Communication
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• v.13 no.3
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• pp.104-108
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• 2021

In order to improve performance in IoT, edge computing system, a memory is usually configured in a hierarchical structure. Based on the distance from CPU, the access speed slows down in the order of registers, cache memory, main memory, and storage. Similar to the change in performance, energy consumption also increases as the distance from the CPU increases. Therefore, it is important to develop a technique that places frequently used data to the upper memory as much as possible to improve performance and energy consumption. However, the technique should solve the problem of cache performance degradation caused by lack of spatial locality that occurs when the data access stride is large. This study proposes a technique to selectively place data with large data access stride to a software-controlled cache. By using the proposed technique, data spatial locality can be improved by reducing the data access interval, and consequently, the cache performance can be improved.

• Industrial Engineering and Management Systems
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• v.9 no.3
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• pp.227-241
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• 2010

A memory module industry's supply chain usually consists of multiple manufacturing sites and multiple distribution centers. In order to fulfill the variety of demands from downstream customers, production planners need not only to decide the order allocation among multiple manufacturing sites but also to consider memory module industrial characteristics and supply chain constraints, such as multiple material substitution relationships, capacity, and transportation lead time, fluctuation of component purchasing prices and available supply quantities of critical materials (e.g., DRAM, chip), based on human experience. In this research, a directed graph-based supply network planning (DGSNP) model is developed for memory module industry. In addition to multi-site order allocation, the DGSNP model explicitly considers production planning for each manufacturing site, and purchasing planning from each supplier. First, the research formulates the supply network's structure and constraints in a directed-graph form. Then, a proposed genetic algorithm (GA) solves the matrix form which is transformed from the directed-graph model. Finally, the final matrix, with a calculated maximum profit, can be transformed back to a directed-graph based supply network plan as a reference for planners. The results of the illustrative experiments show that the DGSNP model, compared to current memory module industry practices, determines a convincing supply network planning solution, as measured by total profit.