• Journal of the Institute of Convergence Signal Processing
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• v.15 no.4
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• pp.169-175
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• 2014

NG-SDH system is connected with networks throughout optical fibers. Network synchronization controller is a necessary for the data synchronization in each optical transmission system. In this paper, we have design and implementation the network synchronization controller using SOPC(system on a programmable chip) design technic. For this network synchronization controller we use FPGA in Altera. FPGA includes 32bit CPU, DPRAM(dual port ram), digital input/output port, transmitter and receiver framer, phase difference detector. We also confirm that designed network synchronization controller satisfies the ITU-T G.813 timing requirements.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.160-169
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• 2002

An ATM-PON (Passive Optical Network) system consists of an OLT (Optical Line Termination), multiple ONUs (Optical Network Units) and the optical fiber which has a PON (Passive Optical Network)configuration with a passive optical splitter. To avoid cell collisions on the upstream transmission, an elaborate procedure called as ranging is needed when a new ONU is installed. The ONU can send upstream cells according to the grant provided by the OLT after the procedure. To prevent collisions being generated by the variation of several factors, OLT must performs continuously the cell phase monitoring. It means that the OLT predicts the expected arrival time, monitors the actual arrival time for all upstream cells and calculates the error between the times. Accordingly, TC (Transmission Convergence) chip in the OLT needs a predictor which predicts the time that the cell will arrive for the current grant. In this paper, we implement the predictor by using shift registers of which the length is equivalent to the equalized round trip delay. As each register consists of 8 bit, OLT can identify which ONU sends what type of cell (ranging cell, user cell, idle cell, and mini-slot). Also, TC chip is designed to calculate the effective bandwidth for all ONUs by using the function of predictor. With the time simulation and the measurement of an implemented optical board, we verify the operation of the predictor.

• Smart Structures and Systems
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• v.12 no.1
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• pp.23-39
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• 2013

In this article, a smart multifunctional optical system-on-a-chip (SOC) sensor platform is presented and its application for fiber Bragg grating (FBG) sensor interrogation in optical sensor networks is investigated. The smart SOC sensor platform consists of a superluminescent diode as a broadband source, a tunable microelectromechanical system (MEMS) based Fabry-P$\acute{e}$rot filter, photodetectors, and an integrated microcontroller for data acquisition, processing, and communication. Integrated with a wireless sensor network (WSN) module in a compact package, a smart optical sensor node is developed. The smart multifunctional sensor platform has the capability of interrogating different types of optical fiber sensors, including Fabry-P$\acute{e}$rot sensors and Bragg grating sensors. As a case study, the smart optical sensor platform is demonstrated to interrogate multiplexed FBG strain sensors. A time domain signal processing method is used to obtain the Bragg wavelength shift of two FBG strain sensors through sweeping the MEMS tunable Fabry-P$\acute{e}$rot filter. A tuning range of 46 nm and a tuning speed of 10 Hz are achieved. The smart optical sensor platform will open doors to many applications that require high performance optical WSNs.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.1526-1531
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• 2007

Data transmission capacity that is required in 2010 is forecasted that increase by optical communication capacity more than present centuple, and is doing increased demand of optical communication related industry product present. Specially, Lid glass' application that is one of optical communication parts is used in optical communication parts manufacture of Fiber array, Ferrule array, Fanout Black, Silica optical waveguide chip and splitter etc. Also, it is used widely for communication network system, CATV, ATM-PON, FTTH and system. But, Lid glass need much processing times and becomes cause in rising prices of optical communication parts because production cost is expensive. The objectives, of this work is to suggest the micro concave and convex pattern manufacturing technology on borosilicate plate using high temperature and compression molding method. As a result, could developed micro pattern Mold more than 5 pattern, and reduce Lid Glass manufacture cycle time.

• Journal of Sensor Science and Technology
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• v.15 no.2
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• pp.112-119
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• 2006

Resolution of an image sensor is very significant parameter to improve. It is hard to improve the resolution of the CMOS vision chip for edge detection based on a biological retina using a resistive network because the vision chip contains additional circuits such as a resistive network and some processing circuits comparing with general image sensors such as CMOS image sensor (CIS). In this paper, we proved the problem of low resolution by separating photo-sensing and signal processing circuits. This type of vision chips occurs a problem of low operation speed because the signal processing circuits should be commonly used in a row of the photo-sensors. The low speed problem of operation was proved by using a reset decoder. A vision chip for edge detection with $128{\times}128$ pixel array has been designed and fabricated by using $0.35{\mu}m$ 2-poly 4-metal CMOS technology. The fabricated chip was integrated with optical lens as a camera system and investigated with real image. By using this chip, we could achieved sufficient edge images for real application.

• Korean Journal of Optics and Photonics
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• v.10 no.6
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• pp.500-506
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• 1999

We designed and fabricated a bidirectional optical transceiver module for low cost access network. An integrated chip forming a pin-PD on an 1.3 urn FP-LD was assembled by flip-chip bonding on a Si optical bench, a single mode fiber with an angled end facet was aligned passively with the integrated chip on V-groove of Si-optical bench. Gaussian beam theory was applied to evaluate the coupling coefficients as a function of some parameters such as alignment distance, angle of fiber end facet, vertical alignment error. The theory is also used to search the bottle-neck between transmittance and receiving coupling efficiency in the bi-directional optical system. Tn this paper, we confirmed that reduction of coupling efficiency by the vertical alignment error between laser beam and fiber core axis can be compensated by controlling the fiber facet angle. In the fabrication of sub-module, a'||'&'||' we made such that the fiber facet have a corn shape with an angled facet only core part, the reflection of transmitted laser beam from the fiber facet could be minimized below -35 dE in alignment distance of 2: 30 /J.m. In the same condition, transmitted output power of -12.1 dEm and responsivity of 0.2. AIW were obtained.

• Proceedings of the Optical Society of Korea Conference
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• 2006.07a
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• pp.207-208
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• 2006

홈 네트워크를 구성하는 여러 분야 중 우리의 삶을 보다 풍요롭고 편리하게 하는, 멀티미디어와 관련된 홈 엔터테인먼트 분야가 강조되면서, 초고속 대용량 데이터의 원활한 전송이 요구되고 있다. 그러나 기존동선 가입자 선로는 이러한 요구를 수용하기에 그 한계에 다다르고 있다. 이로 인해 각 가정까지 광 가입자 선로가 직접 연결되는 FTTH(Fiber To The Home)에 대한 연구가 활발히 수행되고 있으며, 더 나아가 정보가전기기에 광 가입자 선로를 직접 연결하는 방식으로 그 관심이 확장되고 있다. 본 논문에서는 초고속 대용량 데이터의 전송을 위해 광 가입자 선로와 정보가전기기를 직접 연결시키는 방식에서 사용될 수 있는, 정보가전기기에 on-chip 시킬 수 있는 전/광(광/전) 변환 시스템을 설계하고 간략화하여 구현하였다.

• Journal of Korea Multimedia Society
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• v.17 no.3
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• pp.324-332
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• 2014

This paper presents a programmable System-On-a-chip for various embedded applications that need Neural Network computations. The system is fully implemented into Field-Programmable Gate Array (FPGA) based prototyping platform. The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using real image processing applications, such as optical character recognition (OCR) system.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.82-90
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• 2013

An Optical Network-on-Chip(ONoC) based on silicon photonics is one of promising technology for next generation exascale computing architectures. Recent active researches on ONoC focus on improving bandwidth further and avoiding path collisions by using wavelength division multiplexing (WDM). However, the number of wavelengths used for the WDM increases linearly as the number of Processing Element (PE) increases in existing ONoCs which adopt centralized routing architecture. The problem will also arises growing cost of optical devices such as light switches and light sources and limits the scalability of ONoC due to the sinal loss caused by interference of distinct light sources. In this paper, we proposes a distributed routing architecture for ONoC which is based on 2D-mesh structure using WDM technique and present a method that minimize the required number of wavelengths exploiting the connectivity of communication. In comparison with existing centralized routing architectures, results show reduction by 56% of the number of wavelengths and 21% of the number of optical switches in $8{\times}8$ networks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.454-464
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• 2002

In the ATM-PON (Asynchronous Transfer Mode-Passive Optical Network), the downstream cell transmitted by an OLT is broadcast to all ONUs. The ONU receives selectively its own cells by VP filtering. On the other hand, the upstream cell can be transmitted by ONU in the case of receiving a grant from the OLT. After providing the grant to an ONU, the OLT expects the arrival of a cell after an elapse of the equalized round trip delay. ITU-T G.983.1 recommends that one bit error is allowed between the expected arrival time and the actual arrival time at the OLT. Because the ONU processes the different delay to each type of grant (ranging, user cell, and mimi-slot grant), it is not simple to design the transmission part of ONU. In this paper, we implement a grant processor which provides the delay accurately in the ONU TC chip with the FPGA. For the given equalized delay, it deals with the delay for the cell, the byte, and the bit unit by using the shift register, the byte counter, and the D flip-flop, respectively. We verify the operation of the grant processor by the time simulation and the measurement of the optical board output.