• Title/Summary/Keyword: On-chip

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Effects of Cutter Runout on End Milling Forces I-Up Eng Milling- (엔드밀링 절삭력에 미치는 공구형상오차 I- 상향 엔드밀링 -)

  • Lee, Yeong-Mun;Yang, Seung-Han;Song, Tae-Seong;Gwon, O-Jin;Baek, Seung-Gi
    • Journal of the Korean Society for Precision Engineering
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    • v.19 no.8
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    • pp.63-70
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    • 2002
  • In end milling process, the undeformed chip section area and cutting forces vary periodically with phase change of the tool. However the real undeformed chip section area deviates from the geometrically ideal one owing to cutter runout and tool shape error. In this study, a method of estimating the real undeformed chip section area which reflects cutter runout and tool shape error was presented in up end milling process using measured cutting forces. The average specific cutting resistance, Ka is defined as the main cutting force component divided by the modified chip section area. Ka value becomes smaller as the helix angle increases from $30^circC \;to\;40\circC$. But it becomes larger as the helix angle increases from $40^\circ$to 50 . On one hand, the Ka value shows a tendency to decrease with increase of the modified chip section area and this tendency becomes distinct with smaller helix angle.

Real-time Sound Localization Using Generalized Cross Correlation Based on 0.13 ㎛ CMOS Process

  • Jin, Jungdong;Jin, Seunghun;Lee, SangJun;Kim, Hyung Soon;Choi, Jong Suk;Kim, Munsang;Jeon, Jae Wook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.2
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    • pp.175-183
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    • 2014
  • In this paper, we present the design and implementation of real-time sound localization based on $0.13{\mu}m$ CMOS process. Time delay of arrival (TDOA) estimation was used to obtain the direction of the sound signal. The sound localization chip consists of four modules: data buffering, short-term energy calculation, cross correlation, and azimuth calculation. Our chip achieved real-time processing speed with full range ($360^{\circ}$) using three microphones. Additionally, we developed a dedicated sound localization circuit (DSLC) system for measuring the accuracy of the sound localization chip. The DSLC system revealed that our chip gave reasonably accurate results in an experiment that was carried out in a noisy and reverberant environment. In addition, the performance of our chip was compared with those of other chip designs.

The Area Segmentation Pattern Matching for COG Chip Alignment (COG 칩의 얼라인을 위한 영역분할 패턴매칭)

  • KIM EUNSEOK;WANG GI-NAM
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.6
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    • pp.1282-1287
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    • 2005
  • The accuracy of chip alignment in inferior product inspection of COG(Chip On Glass) to be measured a few micro unit is very important role since the accuracy of chip inspection depends on chip alignment. In this paper, we propose the area segmentation pattern matching method to enhance the accuracy of chip alignment. The area segmentation pattern matching method compares, and matches correlation coefficients between the characteristic features within the detailed area and the areas. The three areas of pattern circumference are learned to minimize the matching error by bad pattern. The proposed method has advantage such as reduction of matching time, and enhanced accuracy since the characteristic features are searched within the segmented area.

A Study on the Characteristics Comparison of Single Chip and Two Chip Transceiver for the Fiber Optic Modules (광모듈용 단일 칩 및 2 칩 트랜시버의 특성비교 연구)

  • Chai Sang-Hoon;Jung Hyun-Chae
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.5 s.347
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    • pp.48-53
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    • 2006
  • This paper describes the electrical characteristics of monolithic optical transceiver circuitry being used in the fiber optic modules. It has been designed and fabricated, and compared with two chips version transceiver when operates at 155.52 Mbps data rates. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. To compare the two kind of fiber optic modules using each chip, single chip version has similar properties to two chip version in the electrical characteristics as noise and others.

Effect of Re-oxidation on the Electrical Properties of Mutilayered PTC Thermistors (적층 PTC 써미스터의 전기적 특성에 대한 재산화의 영향)

  • Chun, Myoung-Pyo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.26 no.2
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    • pp.98-103
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    • 2013
  • The alumina substrates that Ni electrode was printed on and the multi-layered PTCR thermistors of which composition is $(Ba_{0.998}Ce_{0.002})TiO_3+0.001MnCO_3+0.05BN$ were fabricated by a thick film process, and the effect of re-oxidation temperature on their resistivities and resistance jumps were investigated, respectively. Ni electroded alumina substrate and the multi-layered PTC thermistor were sintered at $1150^{\circ}C$ for 2 h under $PO_2=10^{-6}$ Pa and then re-oxidized at $600{\sim}850^{\circ}C$ for 20 min. With increasing the re-oxidation temperature, the room temperature resistivity increased and the resistance jump ($LogR_{290}/R_{25}$) decreased, which seems to be related to the oxidation of Ni electrode. The small sized chip PTC thermistor such as 2012 and 3216 exhibits a nonlinear and rectifying behavior in I-V curve but the large sized chip PTC thermistor such as 4532 and 6532 shows a linear and ohmic behavior. Also, the small sized chip PTC thermistor such as 2012 and 3216 is more dependent on the re-oxidation temperature and easy to be oxidized in comparison with the large sized chip PTC thermistor such as 4532 and 6532. So, the re-oxidation conditions of chip PTC thermistor may be determined by considering the chip size.

Study on the Reliability of COB Flip Chip Package using NCP (NCP 적용 COB 플립칩 패키지의 신뢰성 연구)

  • Lee, So-Jeong;Yoo, Se-Hoon;Lee, Chang-Woo;Lee, Ji-Hwan;Kim, Jun-Ki
    • Journal of the Microelectronics and Packaging Society
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    • v.16 no.3
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    • pp.25-29
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    • 2009
  • High temperature high humidity and thermal shock reliability tests were performed for the board level COB(chip-on-board) flip chip packages using self-formulated and commercial NCPs(non-conductive pastes) to ensure the performance of NCP flip chip packages. It was considered that the more smaller fused silica filler in prototype NCPs is more favorable for high temperature high humidity reliability. The failure of NCP interconnection was affected by the expansion of epoxy due to moisture absorption rather than the fatigue due to thermal stress. It was considered that the NCP having more higher adhesive strength seems to be more favorable to increase the thermal shock reliability.

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A 77 GHz mHEMT MMIC Chip Set for Automotive Radar Systems

  • Kang, Dong-Min;Hong, Ju-Yeon;Shim, Jae-Yeob;Lee, Jin-Hee;Yoon, Hyung-Sup;Lee, Kyung-Ho
    • ETRI Journal
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    • v.27 no.2
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    • pp.133-139
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    • 2005
  • A monolithic microwave integrated circuit (MMIC) chip set consisting of a power amplifier, a driver amplifier, and a frequency doubler has been developed for automotive radar systems at 77 GHz. The chip set was fabricated using a 0.15 ${\mu}$ gate-length InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (mHEMT) process based on a 4-inch substrate. The power amplifier demonstrated a measured small signal gain of over 20 dB from 76 to 77 GHz with 15.5 dBm output power. The chip size is 2mm${\times}$ 2mm. The driver amplifier exhibited a gain of 23 dB over a 76 to 77 GHz band with an output power of 13 dBm. The chip size is 2.1mm${\times}$ 2mm. The frequency doubler achieved an output power of -6 dBm at 76.5 GHz with a conversion gain of -16 dB for an input power of 10 dBm and a 38.25 GHz input frequency. The chip size is 1.2mm ${\times}$ 1.2mm. This MMIC chip set is suitable for the 77 GHz automotive radar systems and related applications in a W-band.

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Cutting Chip Forms on the Cutting Condition and Tempering Temperatures of Lead-free Brass (무연황동의 절삭 칩 형태에 미치는 절삭조건과 템퍼링 온도의 영향)

  • Joo, Y.S.;Lee, S.B.;Kim, S.Y.;Joo, C.S.;Jung, B.H
    • Journal of the Korean Society for Heat Treatment
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    • v.25 no.1
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    • pp.14-21
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    • 2012
  • The effects of cutting condition and tempering temperature for the shape of cutting chip were investigated. For this purpose, a lead-free brass containing 1wt.% of Bi extruded at $750^{\circ}C$ in straight turning was used in this study. The cutting chip preferred was mainly found to be loose form of arc chips with curling discontinuity, and these were formed by shear fracture. However, some of fragmental element chip were found to be mixed when tempering temperature was as high as $500^{\circ}C$. The form and size of chip was more affected by feed rate than by tempering temperature and cutting rate. In addition, the cutting surface was observed to be formed more rough in the case of high feed rate and low cutting rate compared to low feed rate and high cutting rate.

Diagnostic Paper Chip for Reliable Quantitative Detection of Albumin using Retention Factor (체류 인자를 이용한, 알부민의 정량 분석용 종이 칩)

  • Jeong, Seong-Geun;Lee, Sang-Ho;Lee, Chang-Soo
    • KSBB Journal
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    • v.28 no.4
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    • pp.254-259
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    • 2013
  • Herein we present a diagnostic paper chip that can quantitatively detect albumin without external electronic reader and dispensing apparatus. We fabricated a diagnostic paper chip device by printing wax barrier on the paper and wicking it with citrate buffer and tetrabromophenol blue to detect albumin in sample solution. The paper chip is so simple that we dropped a sample solution at sample pad and measure the ratio of two travel distances of the sample solvent and albumin under the name of retention factor. Our result confirmed that the retention factor was constant in the samples with same concentration of albumin and useful determinant for the measurement of albumin concentration. The paper chip is affordable and equipment-free, and close to ideal point-of-care test in accordance with the assured criteria, outlined by the World Health Organization. We assume that this diagnostic paper chip will expand the concept of colorimetric determination and provide a inexpensive diagnostic method to aging society and developing country.

Real-time Ray-tracing Chip Architecture

  • Yoon, Hyung-Min;Lee, Byoung-Ok;Cheong, Cheol-Ho;Hur, Jin-Suk;Kim, Sang-Gon;Chung, Woo-Nam;Lee, Yong-Ho;Park, Woo-Chan
    • IEIE Transactions on Smart Processing and Computing
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    • v.4 no.2
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    • pp.65-70
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    • 2015
  • In this paper, we describe the world's first real-time ray-tracing chip architecture. Ray-tracing technology generates high-quality 3D graphics images better than current rasterization technology by providing four essential light effects: shadow, reflection, refraction and transmission. The real-time ray-tracing chip named RayChip includes a real-time ray-tracing graphics processing unit and an accelerating tree-building unit. An ARM Ltd. central processing unit (CPU) and other peripherals are also included to support all processes of 3D graphics applications. Using the accelerating tree-building unit named RayTree to minimize the CPU load, the chip uses a low-end CPU and decreases both silicon area and power consumption. The evaluation results with RayChip show appropriate performance to support real-time ray tracing in high-definition (HD) resolution, while the rendered images are scaled to full HD resolution. The chip also integrates the Linux operating system and the familiar OpenGL for Embedded Systems application programming interface for easy application development.