• 한국통신학회논문지
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• 제34권8C호
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• pp.806-813
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• 2009

본 논문은 고속 무선 통신을 위한 모뎀 설계에 관한 것이다. 고속 통신을 위한 기술에는 여러 가지가 있는데, 그 중 넓은 주파수를 사용하고 여타 서비스에 주파수 간섭을 일으키지 않는 기술인 MB-OFDM (Multi-Band Orthogonal Frequency Division Multiplexing) 방식의 UWB (Ultra-Wideband) 모뎀의 SoC (System-on-Chip) 칩을 설계하였다. 개발된 모뎀 SoC 칩의 기저대역 시스템은 WiMedia에서 정의한 표준안을 따라서 설계되었다. 설계된 SoC 칩은 코어 부분인 FFT/lFFT (Fast Fourier Transform/lnverse Fast Fourier Transform), 송신부, 심볼동기 및 주파수 오프셋 추정부, 비터비 디코더, 그리고 기타 수신부등으로 구성되어 있다. 반도체 공정은 90nm CMOS (Complementary Metal-Oxide-Semiconductor) 공정을 사용하였고, 칩 사이즈는 약 5mm x 5mm 이다. 2009년 7월 20일에 fab-out되었다.

• 한국가시화정보학회지
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• 제1권1호
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• pp.34-37
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• 2003

• 한국정보과학회논문지:시스템및이론
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• 제36권2호
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• pp.102-110
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• 2009

컴퓨터 시스템 분야의 대표적인 문제 중 하나는 메모리의 처리 속도가 CPU의 처리 속도보다 매우 느리기 때문에 생기는 CPU 휴면 시간의 증가, 즉 메모리 장벽 문제이다. CPU와 메모리의 속도 차이를 줄이기 위해서는 레지스터, 캐시 메모리, 메인 메모리, 디스크로 대표되는 메모리 계층을 이용하여 자주 쓰이는 데이터를 메모리 계층 상위, 즉 CPU 가까이 위치시켜야 한다. 본 논문에서는 On-Chip SRAM을 이용한 임베디드 시스템 메모리 계층 최적화 기법을 리눅스 기반 시스템에서 최초로 제안한다. 본 기법은 시스템의 가상 메모리를 이용하여 프로그래머가 원하는 코드나 데이터를 On-Chip SRAM에 적재한다. 제안된 기법의 실험 결과 총 9개의 어플리케이션에 대하여 최대 35%, 평균 14%의 시스템 성능 향상과 최대 40% 평균 15%의 에너지 소비 감소를 보였다.

• ETRI Journal
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• 제27권1호
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• pp.81-88
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• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.

• ETRI Journal
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• 제28권4호
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• pp.525-528
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• 2006

In this letter, we present a design of a single chip video decoder called advanced mobile video ASIC (A-MoVa) for mobile multimedia applications. This chip uses a mixed hardware/software architecture to improve both its performance and its flexibility. We designed the chip using a partition between the hardware and software blocks, and developed the architecture of an H.264 decoder based on the system-on-a-chip (SoC) platform. This chip contains 290,000 logic gates, 670,000 memory gates, and its size is $7.5\;mm{\times}7.5\;mm$ (using 0.25 micron 4-layers metal CMOS technology).

• Journal of Information Display
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• 제13권1호
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• pp.1-6
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• 2012

Decreasing the thermal resistance is the critical issue for high-brightness light-emitting diodes. In this paper, the effects of some design factors, such as chip size (24 and 35 mil), substrate material (AlN and high-temperature co-fired ceramic), and die-attach material (Ag epoxy and PbSn solder), on the thermal-dissipation characteristics were investigated. Using the thermal transient method, the temperature sensitivity parameter, $R_{th}$ (thermal resistance), and junction temperature were estimated. The 35-mil chip showed better thermal dissipation, leading to lower thermal resistance and lower junction temperature, owing to its smaller heat source density compared with that of the 24-mil chip. By adopting an AlN substrate and a PbSn solder, which have higher thermal conductivity, the thermal resistance of the 24-mil chip can be decreased and can be made the same as that of the 35-mil chip.

• Transactions on Electrical and Electronic Materials
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• 제5권4호
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• pp.138-142
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• 2004

This paper presents the improved bum-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved through the bum-in process. Reliability problem is more significant in MCP that includes over two chips in a package, because the failure of one chip (SRAM) has a large influence on the yield and quality of the other chips - Flash Memory, DRAM, etc. Therefore, the quality of SRAM must be guaranteed. To improve the quality of SRAM, we applied the improved wafer level bum-in process using multi cells selection method in addition to the previously used methods. That method is effective in detecting special failure. Finally, with the composition of some kind of methods, we could achieve the high quality of SRAM in Multi Chip Package.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.1187-1188
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• 2008

An area of research called evolvable hardware has recently emerged which combines aspects of evolutionary computation with hardware design and synthesis. Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer. In this paper, we have studied and surveyed a gate-level evolvable hardware chip, by integrating both GA hardware and reconfigurable hardware within a single LSI chip. The chip consists of genetic algorithm(GA) hardware, reconfigurable hardware logic, and the control logic. In this paper, we describe the architecture, functions of the chip.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1997년도 추계학술대회 논문집
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• pp.973-976
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• 1997

Process behavior in metal cutting results from the chip formation process which is not easily observable and measurable during machining. By means of the finite element method chip formation in orthogonal metal cutting is modeled. The reciprocal interaction between mechanical and thermal loads is taken into consideration by involving the thermo-viscoplastic flow behavior of workpiece material. Local and temporal distributions of stress and temperature in the cutting zone are calculated depending on the cutting parameters. The calculated cutting forces and temperatures are compared with the experimental results obtarned from orthogonal cutting of steel AISl 4140. The model can be applied in process design for selection of appropriate tool-workpiece combination and optimum cutting conditions in term of mechanical and thermal loads.

• Bulletin of the Korean Chemical Society
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• 제26권3호
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• pp.379-383
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• 2005

This research aims to develop DNA chip array without an indicator. We fabricated microelectrode array by photolithography technology. Several DNA probes were immobilized on an electrode. Then, indicator-free target DNA was hybridized by an electrical force and measured electrochemically. Cyclic-voltammograms (CVs) showed a difference between DNA probe and mismatched DNA in an anodic peak. Immobilization of probe DNA and hybridization of target DNA could be confirmed by fluorescent. This indicator-free DNA chip microarray resulted in the sequence-specific detection of the target DNA quantitatively ranging from $10^{-18}\;M\;to\;10^{-5}$ M in the buffer solution. This indicator-free DNA chip resulted in a sequence-specific detection of the target DNA.