• Journal of electromagnetic engineering and science
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• v.11 no.4
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• pp.282-289
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• 2011

GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

• The Journal of Asian Finance, Economics and Business
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• v.7 no.12
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• pp.783-793
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• 2020

This research investigates the explanatory factors governing the dividend payout to shareholders of blue-chip companies listed on Bursa Malaysia. In spite of continuous attention offered by empirical research on dividend payout of publicly-listed companies, paradoxically only few studies exclusively examined the explanatory factors from the perspective of blue-chip companies. Recognizing the capability of blue-chip companies to serve as a stalwart indicator of stock market condition as well as a consistent income source to shareholders, more research should be carried out for better inference on the companies' dividend payout decision. This research is using 522 observations from a sample of 18 Malaysian blue-chip companies over a 29-year period (1990 to 2019) and utilizes a panel data regression analysis for the estimation of the impact of eight factors, namely, systematic risk, leverage, free cash flow, lagged dividends, market-to-book value, profit growth, total asset turnover, and company size. Measuring dividend payout using two specifications (dividend/earnings and dividend/total assets), this research reveals that systematic risk and free cash flow have a significant and negative impact on dividend payout. Meanwhile, past year dividends, market-to-book value, profit growth, total asset turnover and company size have a significant and positive impact on dividend payout.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1295-1297
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• 1996

CCITT G.721, G.723 standard ADPCM algorithm is implemented by using TI's fixed point DSP start kit (DSK). ADPCM can be implemented on a various rates, such as 16K, 24K, 32K and 40K. The ADPCM is sample based compression technique and its complexity is not so high as the other speech compression techniques such as CELP, VSELP and GSM, etc. ADPCM is widely applicable to most of the low cost speech compression application and they are tapeless answering machine, simultaneous voice and fax modem, digital phone, etc. TMS320C50 DSP is a low cost fixed point DSP chip and C50 DSK system has an AIC (analog interface chip) which operates as a single chip A/D and D/A converter with 14 bit resolution, C50 DSP chip with on-chip memory of 10K and RS232C interface module. ADPCM C code is compiled by TI C50 C-compiler and implemented on the DSK on-chip memory. Speech signal input is converted into 14 bit linear PCM data and encoded into ADPCM data and the data is sent to PC through RS232C. The ADPCM data on PC is received by the DSK through RS232C and then decoded to generate the 14 bit linear PCM data and converted into the speech signal. The DSK system has audio in/out jack and we can input and out the speech signal.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.13-14
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• 2012

• Journal of the Korean Society for Precision Engineering
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• v.17 no.11
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• pp.25-35
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• 2000

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.149-158
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• 1996

In this paper we describe designing and implementing a digital neural chip and a parallel neural machine for simulating large scale neural netsorks. The chip is a single-chip multiprocessor which has four digiral neural processors (DNP-II) of the same architecture. Each DNP-II has program memory and data memory, and the chip operates in MIMD (multi-instruction, multi-data) parallel processor. The DNP-II has the instruction set tailored to neural computation. Which can be sed to effectively simulate various neural network models including on-chip learning. The DNP-II facilitates four-way data-driven communication supporting the extensibility of parallel systems. The parallel neural machine consists of a host computer, processor boards, a buffer board and an interface board. Each processor board consists of 8*8 array of DNP-II(equivalently 2*2 neural chips). Each processor board acn be built including linear array, 2-D mesh and 2-D torus. This flexibility supports efficiency of mapping from neural network models into parallel strucgure. The neural system accomplishes the performance of maximum 40 GCPS(giga connection per second) with 16 processor boards.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.32 no.9
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• pp.720-727
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• 2008

Microfluidic single chip integrating thermopneumatic micropump and micro check valve are developed. The micropump and micorvalve are made of biocompatible materials, glass and PDMS, so as to be applicable to the biochip. By using the passive-type check valve, backward flow and fluid leakage are blocked and flow control is stable and precise. The chip is composed of three PDMS layers and a glass substrate. In the chip, flow channel and pump chamber were made on the PDMS layers by the replica molding technique and pump heater was made on the glass substrate by Cr/Au deposition. Diameter of the pump chamber is 7 mm and the width and depth of the channel are 200 and $180{\mu}m$, respectively. The PDMS layers chip and the heater deposited glass chip are combined by a jig and a clamp for pumping operation, and they are separable so that PDMS chip is used as a disposable but the heater chip is able to be used repeatedly. Pumping performance was simulated by CFD software and investigated experimentally. The performance was the best when the duty ratio of the applied voltage to the heater was 33%.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.10
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• pp.676-681
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• 2015

Recently many studies being carried out to increase the light efficiency of LED. The external quantum efficiency of LED, generally the light efficiency, is determined by the internal quantum efficiency and the light extraction efficiency. The internal quantum efficiency of LED was already reached to more than 90%, but the light extraction efficiency is still insufficient compared with the internal quantum efficiency because the total internal reflection is generated in the interface between the LED chip and air. Thus, we studied about flip chip LED with PSS and performed the optical simulation which find more optimized PSS for flip chip LED to increase the light extraction efficiency. Decreasing of the total internal reflection and effect of diffused reflection according to PSS improved the light extraction efficiency. To get more higher the efficiency, we simulated flip chip with PSS that the parameters are arrangement, edge spacing, radius, height and shape of PSS.

• Proceedings of the KSME Conference
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• 2001.06d
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• pp.546-552
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• 2001

The heat transfer and flow measurements on a pedestal encountered in chip cooling. A uniform wall temperature boundary condition at the plate surface and on a pedestal was created using shroud method. Liquid crystal was used to measure the plate surface temperature. The jet Reynolds number (Re) ranges from 11,000 to 50,000, the dimensionless nozzle-to-surface distance (L/d) from 2 to 10, and the dimensionless pedestal diameter-to-height (H/D) from 0 to 1.0. The results show that the Nusselt number distributions at the near the pedestal exhibit secondary maxima at $r/d{\cong}1.0\;and\;1.5$. The formation of the secondary maxima is attributed to an create in the vortex by the pedestal.

• Proceedings of the KIEE Conference
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• 2002.11a
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• pp.263-265
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• 2002

We have used the secondary-step immobilization methods based on the chip pattern of hydrophobic self-assembly layers to assemble microfabricated particles onto the chip pattern. Immobilization of DNA, fabrication of the particles and the chip pattern, arrangement of the particles on the chip pattern, and recognition of each using DNA fluorescence measurement were carried out. Establishing the walls, the arrangement stability of the particles was improved. Each DNA is able to distinguish by using the lithography process on the particles. Advantages of this method are process simplicity, wide applicability and stability. It is thought that this method can be applicable as a new fabrication technology to develop a minute integration type biosensor microarray.