• 한국산업융합학회 논문집
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• 제15권2호
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• pp.55-58
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• 2012

This study is concerned about the design and structural analysis of high integrated Chip Bonding Machine. Recently, many studies have been undergoing to reduce a working time in a field of Chip Bonding Machine. Chip Bonding Machine belongs to reduce a stand-by time by Chip Moving time. The developed system can save tool moving distance in small space than other machine. The analysis is carried out by SoldEdge & Ansys software.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2007년 추계학술발표대회 개요집
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• pp.218-221
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• 2007

The surface mounting technology of 0402 electric chip part is necessary to fabricate a high density and multi-functional module, but there is a limitation of the technology, like as a bridge and self-alignement. This work estimated SMT processing factors of 0402 chip. To obtain optimum SMT process, we evaluated effects of stencil thickness, shape of hole on printability and mountability. Printability shows best results under the thickness of $80{mu}m$ with circle hole shape and 90% square hole shape. In case of chip mounting process, chip mis-alignment and bridge was occurred rarely in same conditions. In more thin stencil thickness, $50{mu}m$, strength of 1005 chip parts was poor, because of amount of printed solder was insufficient.

• 전자통신동향분석
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• 제36권3호
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• pp.1-11
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• 2021

In this study, we analyze the automotive chip ecosystem that recently caused the global supply shortage, and attempt to derive policy implications for us from the conclusion. Automotive chips are critical parts that control various systems so that a vehicle can drive itself or operate with electricity. The current shortage in supply and demand for automotive chips is due to the inconsistency between supply and demand between automotive chip companies and car manufacturers. To promote the automotive chip industry, new investment incentives, tax cuts, and human resource training are needed.

• 마이크로전자및패키징학회지
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• 제27권4호
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• pp.1-10
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• 2020

웨어러블 소자를 구현하기 위한 칩-섬유 접합 기술을 중심으로 전자 섬유에 대한 기술 개발 동향을 소개한다. 전자 부품을 섬유에 접합하기 위해서는 먼저 전자 부품에 전원 공급 및 전기적 신호를 주고 받기 위한 회로를 섬유에 구성해야 하며, 회로의 해상도와 밀도에 따라 전도성 실을 이용하는 자수법 또는 전도성 페이스트 등을 이용한 프린트법을 통해 구현할 수 있다. 전자 부품과 섬유를 접합하기 위해서는 솔더링, ACF/NCA, 자수법, 크림핑 등의 방법을 이용하여 영구적으로 접합하거나 후크, 자석, 지퍼 등을 이용하여 탈부착이 가능하도록 접합하는 방법이 있으며, 접합 배선의 밀도 및 용도에 따라서 단독 또는 융합하여 사용한다. 접합 이후에는 방수 등 사용환경에서의 신뢰성을 확보하기 위해 encapsulation 작업을 수행해야 하며, 현재는 PDMS 등의 폴리머를 이용한 방법이 널리 쓰이고 있다.

• Animal cells and systems
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• 제14권1호
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• pp.1-10
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• 2010

Previously we showed that CHIP, a co-chaperone of Hsp70 and E3 ubiquitin ligase, can promote the degradation of mutant SOD1 linked to familial amyotrophic lateral sclerosis (fALS) via a mechanism not involving SOD1 ubiquitylation. Here we present evidence that CHIP functions in the interaction of mutant SOD1 with 26S proteasomes. Bag-1, a coupling factor between molecular chaperones and the proteasomes, formed a complex with SOD1 in an hsp70-dependent manner but had no direct effect on the degradation of mutant SOD1. Instead, Bag-1 stimulated interaction between CHIP and the proteasome-associated protein VCP (p97), which do not associate normally. Over-expressed CHIP interfered with the association between mutant SOD1 and VCP. Conversely, the binding of CHIP to mutant SOD1 was inhibited by VCP, implying that the chaperone complex and proteolytic machinery are competing for the common substrates. Finally we observed that mutant SOD1 strongly associated with the 19S complex of proteasomes and CHIP over-expression specifically reduced the interaction between S6/S6' ATPase subunits and mutant SOD1. These results suggest that CHIP, together with ubiquitin-binding proteins such as Bag-1 and VCP, promotes the degradation of mutant SOD1 by facilitating its translocation from ATPase subunits of 19S complex to the 20S core particle.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.376-379
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• 2001

In this paper, I design the control chip that controls inner test sequence of Logic Tester to test chip. Logic tester has the thirteen inner instructions to control test sequence in test. And these instructions are saved in memory with test pattern data. Control chip generates address and control signal such as read, write signal of memory. Before testing, necessary data such as start address, end address, etc. are written to inner register of control chip. When test started, control chip receives the instruction in start address and executes, and generates address and control signals to access tester' inner memory. So whole test sequence is controlled by making the address and control signal in tester's inner memory. Control chip designs instruction's execution blocks, respectively. So if inner instruction is added from now on, a revision is easy. The control chip will be made using FPGA of Xilinx Co. in future.

• Journal of information and communication convergence engineering
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• 제6권2호
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• pp.122-128
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• 2008

Multiprocessor architectures and platforms, such as, a multiprocessor system on chip (MPSoC) recently introduced to extend the applicability of the Moore's law, depend upon concurrency and synchronization in both software and hardware to enhance design productivity and system performance. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and non-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future System-on-Chip (SoC). We have modeled a concurrent architecture for a customizable and scalable NOC in a system level modeling environment using MLDesigner (from MLD Inc.). Varying network loads under various traffic scenarios were applied to obtain realistic performance metrics. We provide the simulation results for latency as a function of the buffer size. We have abstracted the area results for NOC components from its FPGA implementation. Modeled NOC architecture supports three different levels of quality-of-service (QoS).

• 한국지능시스템학회논문지
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• 제10권3호
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• pp.270-279
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• 2000

본 논문은 확률 펄스연산을 이용한 신경회로망이 on-Chip학습 알고리즘에 대해 기술하였다. 확률 펄스 연산은 임이의 펄스열에서 1과 0이 발생할 확률을 통해 표현된 수를 사용하여 계산하는 것을 일컫는다. 이러한 확률연산을 신경회로망에 적용하면 하드웨어 구현먼적을 줄일 수 있다는 것과 확률적인 특징으로 인해 지역 최소값으로부터 빠져 나와 광역 최적해에 도달할 수 있다는 장점을 갖고 있다. 또한 본 연구에서는 칩 냅에 학습할 수 있는 on-chip학습 알고리즘을 역전파 학습 알고리즘으로부터 유도하였다. 이렇게 유도된 알고리즘을 검증하기 위하여 비선형 패턴분리문제를 모의실험 하였다. 도한 활자체 및 필기체 숫자 인식에도 적용하여 좋은 결과를 얻었다.

• ETRI Journal
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• 제33권3호
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• pp.335-343
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• 2011

The pad pitch of modern radio frequency integrated circuits is in the order of few tens of micrometers. Connecting a large number of high-speed I/Os to the outside world with good signal fidelity at low cost is an extremely challenging task. To cope with this requirement, we need reflection-free transmission lines from an on-chip pad to on-board SMA connectors. Such a transmission line is very hard to design due to the difference in on-chip and on-board feature size and the requirement for extremely large bandwidth. In this paper, we propose the use of narrow tracks close to chip and wide tracks away from the chip. This narrow-to-wide transition in width results in impedance discontinuity. A step change in substrate thickness is utilized to cancel the effect of the width discontinuity, thus achieving a reflection-free microstrip. To verify the concept, several microstrips were designed on multilayer FR4 PCB without any additional manufacturing steps. The TDR measurements reveal that the impedance variation is less than 3 ${\Omega}$ for a 50 ${\Omega}$ microstrip and S11 better than -9 dB for the frequency range 1 GHz to 6 GHz when the width changes from 165 ${\mu}m$ to 940 ${\mu}m$, and substrate thickness changes from 100 ${\mu}m$ to 500 ${\mu}m$.

• KIEE International Transactions on Electrophysics and Applications
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• 제4C권4호
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• pp.133-136
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• 2004

This research aims to develop a DNA chip array without an indicator. We fabricated a microelectrode array through photolithography technology. Several DNA probes were immobilized on an electrode. Then, target DNA was hybridized and measured electrochemically. Cyclic-voltammograms (CVs) showed a difference between the DNA probe and mismatched DNA in an anodic peak. This indicator-free DNA chip resulted in a sequence-specific detection of the target DNA.