• 제목/요약/키워드: OES(optical omission spectroscopy)

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SiON 박막의 광학적 특성에 대한 연구 (The study of SiON thin film for optical properlies)

  • 김도형;임기주;김기현;김현석;김상식;성만영
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 추계학술대회 논문집
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    • pp.247-250
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    • 2001
  • We studied optical properties of SiON thin-film in the applications of optical waveguide. SiON thin-film was grown in 300$^{\circ}C$ by PECVD(plasma enhanced chemical vapor deposition) system. The change of SiON thin-film composition and refractive Index was studied as a function of varying NH$_3$ gas flow rate. As NH$_3$ gas flow rate was increased, Quantity of N and refractive index were increased at the same time. By the results, we could form the SiON thin-film to use of a waveguide with refractive index of 1.6. We analyzed the conditions of the thin-film with FTIR(fourier transform infrared) and OES(optical emission spectroscopy). N-H bonding(3390cm$\^$-1/) can be removed by thermal annealing. And we could observe the SiH bonding state and quantity by OES analysis in SiH$_4$

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90 nm급 텅스텐 폴리사이드 게이트 식각공정에서 식각종말점의 안정화에 관한 연구 (A Study for Stable End Point Detection in 90 nm WSix/poly-Si Stack-down Gate Etching Process)

  • 고용득;천희곤;이징혁
    • 한국전기전자재료학회논문지
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    • 제18권3호
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    • pp.206-211
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    • 2005
  • The device makers want to make higher density chips on the wafer through scale-down. The change of WSix/poly-Si gate film thickness is one of the key issues under 100 nm device structure. As a new device etching process is applied, end point detection(EPD) time delay was occurred in DPS+ poly chamber of Applied Materials. This is a barrier of device shrink because EPD time delay made physical damage on the surface of gate oxide. To investigate the EPD time delay, the experimental test combined with OES(Optical Emission Spectroscopy) and SEM(Scanning Electron Microscopy) was performed using patterned wafers. As a result, a EPD delay time is reduced by a new chamber seasoning and a new wavelength line through plasma scan. Applying a new wavelength of 252 nm makes it successful to call corrected EPD in WSix/poly-Si stack-down gate etching in the DPS+ poly chamber for the current and next generation devices.