• 제목/요약/키워드: O&M cost

검색결과 328건 처리시간 0.03초

Enhancement of Electrochemical Activity of Ni-rich LiNi0.8Mn0.1Co0.1O2 by Precisely Controlled Al2O3 Nanocoatings via Atomic Layer Deposition

  • Ramasamy, Hari Vignesh;Sinha, Soumyadeep;Park, Jooyeon;Gong, Minkyung;Aravindan, Vanchiappan;Heo, Jaeyeong;Lee, Yun-Sung
    • Journal of Electrochemical Science and Technology
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    • 제10권2호
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    • pp.196-205
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    • 2019
  • Ni-rich layered oxides $Li(Ni_xCo_yMn_z)O_2$ (x + y + z = 1) have been extensively studied in recent times owing to their high capacity and low cost and can possibly replace $LiCoO_2$ in the near future. However, these layered oxides suffer from problems related to the capacity fading, thermal stability, and safety at high voltages. In this study, we use surface coating as a strategy to improve the thermal stability at higher voltages. The uniform and conformal $Al_2O_3$ coating on prefabricated electrodes using atomic layer deposition significantly prevented surface degradation over prolonged cycling. Initial capacity of 190, 199, 188 and $166mAh\;g^{-1}$ is obtained for pristine, 2, 5 and 10 cycles of ALD coated samples at 0.2C and maintains 145, 158, 151 and $130mAh\;g^{-1}$ for high current rate of 2C in room temperature. The two-cycle $Al_2O_3$ modified cathode retained 75% of its capacity after 500 cycles at 5C with 0.05% capacity decay per cycle, compared with 46.5% retention for a pristine electrode, at an elevated temperature. Despite the insulating nature of the $Al_2O_3$ coating, a thin layer is sufficient to improve the capacity retention at a high temperature. The $Al_2O_3$ coating can prevent the detrimental surface reactions at a high temperature. Thus, the morphology of the active material is well-maintained even after extensive cycling, whereas the bare electrode undergoes severe degradation.

80296SA를 이용한 영구자석 동기전동기 벡터제어의 완전 디지털화 (A fully digitized Vector Control of PMSM using 80296SA)

  • 안영식;배정용;이홍희
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 1998년도 연구회 합동 학술발표회 논문집
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    • pp.5-8
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    • 1998
  • The adaptation to vector control theory is so generalized that it is widely used for implementing the high-performance of AC machine. Nowadays, One-Chip microprocessors or DSP chips are being well-used to implement Vector Control algorithm. DSP Chip have less flexibility for memory decoding and I/O rather than One-Chip microprocessor so that is requires more additional circuit and high cost. And the past One-Chip micro processors have difficult of implementation the complex algorithm because of small memory capacity and low arithmetic performance. Therefore we implemented the vector control algorithm of PMSM(Permanent Magnetic Synchronous Motors) using 80296SA form intel , which have many features as 6M memory space, 500MHz clock frequency, including memory decoding circuit and general I/O, Special I/O(EPA, Interrupt controller, Timer/Count, PWM generator) which is proper controller for the complex algorithm or operation program requiring so much memory capacity, So in this paper we fully digitized the vector control of PMSM included SVPWM Voltage controller using the intel 80296SA

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비용 제약조건을 이용한 병렬 O(n!) 서치 스페이스 탐색 기법의 구현 (Implementation of a parallel traversal scheme for O(n!) search space exploiting cost constraint)

  • 이정훈
    • 한국정보처리학회:학술대회논문집
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    • 한국정보처리학회 2010년도 추계학술발표대회
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    • pp.1501-1502
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    • 2010
  • DualCore 혹은 MultiCore 플랫폼의 보급에 따라 높은 시간복잡도를 갖는 응용들도 사용자의 컴퓨터나 단말에서 수행되어 다양한 서비스를 제공할 수 있게 되었다. 본 논문에서는 관광 스케줄을 효율적으로 결정하기 위한 다중목적지 방문 문제에 대해 이중 쓰레드에 기반한 서치 스페이스 탐색 알고리즘을 구현한다. 이는 Traveling Salesman Problem의 한 종류로서 O(n!) 시간 복잡도를 갖고 있으며 검색시의 독립성때문에 각 쓰레드는 병렬적으로 최적의 스케줄을 탐색할 수 있다. 또 현재까지 발견된 최적값을 기반으로 부분 경로의 비용이 이미 최적값을 넘는 경우는 하위 탐색을 제거하여 상당한 성능의 향상을 가져온다. 2.4 GHz Intel(R) Core DuoCPU와 3 GB 메모리로 구성된 플랫폼 상에서 구현된 서비스는 11개의 목적지에 대한 방문 스케줄을 생성함에 있어서 단일 쓰레드 버전은 14.196초, 이중 쓰레드 버전은 6.411초, 제약조건을 포함한 이중 쓰레드 버전은 0.14초에 최적의 스케줄을 찾아낼 수 있다.

Room-Temperature Luminescence from Ion Beam or Atmospheric Pressure Plasma-Treated SrTiO3

  • Song, J.H.;Choi, J.M.;Cho, M.H.;Choi, E.J.;Kim, J.;Song, J.H.
    • Applied Science and Convergence Technology
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    • 제23권5호
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    • pp.261-264
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    • 2014
  • $SrTiO_3$ (STO) single crystal irradiated with a 3-MeV proton beam exhibits blue and green mixed luminescence. However, the same proton beam when used to irradiate STO with a very thin layer of deposited Pt does not show any luminescence. This Pt layer prevents any damage which may otherwise be caused by arcing, which stems from the accumulated surface voltage of tens of kV due to the charge induced by secondary electrons on the surface of the insulator during the ion beam irradiation process. Hence, the luminescence of ion-irradiated STO originates from the modification of the STO surface layer caused by arcing rather than from any direct ion beam irradiation effect. STO treated with atmospheric-pressure plasma, a simple and cost-effective method, also exhibits the same type of blue and green mixed luminescence as STO treated with an ion beam, as the plasma also creates a layer of surface damage due to arcing.

해상풍력발전의 에너지단가(COE)절감 시나리오 연구 (Study on Cost of Energy(COE) Reduction Scenario of Korean Offshore Wind Power)

  • 성진기;이종훈;강금석;이태진
    • 전기학회논문지
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    • 제62권11호
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    • pp.1520-1527
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    • 2013
  • The purpose of this study is to derive COE reduction targets of offshore wind power in Korea. In addition, innovation factors for achieving the COE reduction targets were derived. Also the COE reduction targets of offshore wind power was to improve that national policy, technology, industry and improving regulations would like to help. The results of this study has been created based on the various assumptions, scenarios and experts' discussions. Currently, offshore wind power generation price is 229.72won/kWh in 2012. According to the study, COE of offshore wind power has been proposed 88.8won/kWh at third scenario by 2030. This result has shown competitiveness with fossil fuel power generation.

BUMPLESS FLIP CHIP PACKAGE FOR COST/PERFORMANCE DRIVEN DEVICES

  • Lin, Charles W.C.;Chiang, Sam C.L.;Yang, T.K.Andrew
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2002년도 International Symposium
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    • pp.219-225
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    • 2002
  • This paper presents a novel "bumpless flip chip package"for cost! performance driven devices. Using the conventional electroplating and etching processes, this package enables the production of fine pitch BGA up to 256 I/O with single layer routing. An array of circuitry down to $25-50{\mu}{\textrm}{m}$ line/space is fabricated to fan-in and fan-out of the bond pads without using bumps or substrate. Various types of joint methods can be applied to connect the fine trace and the bond pad directly. The resin-filled terminal provides excellent compliancy between package and the assembled board. More interestingly, the thin film routing is similar to wafer level packaging whereas the fan-out feature enables high lead count devices to be accommodated in the BGA format. Details of the design concepts and processing technology for this novel package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with die-level and system-level design teams is highlighted as critical to an optimal design for performance and cost.

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SSD 캐시를 적용한 HDFS의 I/O 비용 기반 데이터 선택 기법 (Mechanism to Select the Data Source of HDFS with SSD Cache Based on Storage I / O Cost)

  • 김민정;신민철;박상현
    • 한국정보처리학회:학술대회논문집
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    • 한국정보처리학회 2015년도 춘계학술발표대회
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    • pp.676-679
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    • 2015
  • 빅데이터 분석을 위한 Hadoop 환경에서 고성능 저장장치인 SSD에 대한 중요성이 증가하면서 일반적으로 사용되는 저장장치인 HDD와 혼합하여 사용하는 연구들이 주목 받고 있다. 특히 SSD를 HDD의 캐시로 사용했을 때 저장장치에 대한 I/O 성능을 향상할 수 있다는 연구 결과들이 있다. 본 연구는 이를 바탕으로 SSD를 HDD의 캐시로 사용한다. HDFS는 저장장치에 접근하여 I/O를 수행하는데 기존에는 로컬 서버에서 캐시 미스가 발생한 경우 로컬 HDD로 접근한다. 이러한 방식은 접근하는 데이터에 따라 SSD의 높은 Bandwidth를 활용하지 못하게 되는 경우를 발생시키고 그 결과 특정 서버의 I/O 지연으로 전체 분산 처리의 성능을 저하시킬 수 있다. 이를 해결하기 위해 본 연구는 HDFS 레벨에서 로컬 서버의 HDD와 데이터 복제본들이 저장된 원격 서버의 SSD에서 I/O를 수행하는 경우에 대해 수식을 통해 비용을 비교한다. 그 결과 항상 기대 성능이 높은 저장 장치를 선택하여 데이터를 읽어오게 함으로써 기존 방식보다 성능이 개선될 수 있음을 입증한다.

DEVELOPMENT AND IMPLEMENTATION OF DISTRIBUTED HARDWARE-IN-THE-LOOP SIMULATOR FOR AUTOMOTIVE ENGINE CONTROL SYSTEMS

  • YOON M.;LEE W.;SUNWOO M.
    • International Journal of Automotive Technology
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    • 제6권2호
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    • pp.107-117
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    • 2005
  • A distributed hardware-in-the-loop simulation (HILS) platform is developed for designing an automotive engine control system. The HILS equipment consists of a widely used PC and commercial-off-the-shelf (COTS) I/O boards instead of a powerful computing system and custom-made I/O boards. The distributed structure of the HILS system supplements the lack of computing power. These features make the HILS equipment more cost-effective and flexible. The HILS uses an automatic code generation extension, REAL-TIME WORKSHOP$^{ (RTW$^{) of MATLAB$^{ tool-chain and RT-LAB$^{, which enables distributed simulation as well as the detection and generation of digital event between simulation time steps. The mean value engine model, which is used in control design phase, is imported into this HILS. The engine model is supplemented with some I/O subsystems and I/O boards to interface actual input and output signals in real-time. The I/O subsystems are designed to imitate real sensor signals with high fidelity as well as to convert the raw data of the I/O boards to the appropriate forms for proper interfaces. A lot of attention is paid to the generation of a precise crank/ earn signal which has the problem of quantization in a conventional fixed time step simulation. The detection of injection! command signal which occurs between simulation time steps are also successfully compensated. In order to prove the feasibility of the proposed environment, a simple PI controller for an air-to-fuel ratio (AFR) control is used. The proposed HILS environment and I/O systems are shown to be an efficient tool to develop various control functions and to validate the software and hardware of the engine control system.

100 m급 Bi-2223 고온초전도 선재 제조 및 특성 (Fabrication and performance of 100 m Class Bi-2223 High Temperature Superconducting Tape)

  • 하홍수;오상수;하동우;장현만;이남진;류강식;이준석
    • 한국초전도ㆍ저온공학회논문지
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    • 제1권2호
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    • pp.15-19
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    • 1999
  • For large scale applications of high temperature superconductor (HTS) such as transmission cables, motors and generators, long length of flexible HTS conductor is required. Currently, Bi-2223 HTS tape is capable of being fabricated in longer than 100 m length by industrial processes. In this study, we fabricated 100 m 19 filamentary Bi-2223 ($Bi_{1.8}Pb_{0.4}Sr_2Ca_2O_{10+x}$) HTS tape by PIT (Power in Tube) process. Critical current(IC) of this long length tape was measured 18.5 A at 77K, self field. Critical current of 100 m length tape was mainly resulted from the increase of inhomogeneity in oxide from the increase of inhomogeneity in oxide layer. Engineering critical current (Je=Ic/total tape cross-section area) that is important factor for practical applications and fabrication cost was measured 2.2 kA/cm2.

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An Allocation Problem in a Certain Class of Flexible Manufacturing Systems

  • Kim, Sung-Chul
    • 한국경영과학회지
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    • 제13권1호
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    • pp.24-30
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    • 1988
  • We study the optimal allocation of machines and pallets in a class of manufacturing systems. The FMS is modeled as a closed queueing network with balanced loading of the stations. An Algorithm is developed, which exploits the properties of the throughput function and solves the allocation problem for increasing concave profit and convex cost. We also study the more general case of allocating machines and pallets among a set of FMSs. A dynamic programming approach is developed, which solves the problem with O(M$^{3}$N$^{2}$) operations.

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