• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.440-440
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• 2011

We report on the non-volatile memory characteristics of a bistable organic memory (BOM) device with Au nanoparticles (NPs) embedded in a conducting poly N-vinylcarbazole (PVK) colloids hybrid layer deposited on flexible polyethylene terephthalate (PET) substrates. Transmission electron microscopy (TEM) images show the Au nanoparticles distributed isotropically around the surface of a PVK colloid. The average induced charge on Au nanoparticles, estimated using the C-V hysteresis curve, was large, as much as 5 holes/NP at a sweeping voltage of ${\pm}3$ V. The maximum ON/OFF ratio of the current bistability in the BOM devices was as large as $1{\times}105$. The cycling endurance tests of the ON/OFF switching exhibited a high endurance of above $1.5{\times}105$ cycles and a high ON/OFF ratio of ~105 could be achieved consistently even after quite a long retention time of more than $1{\times}106$ s.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.20-20
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• 2007

Nanowire-based field-effect transistors (FETs) decorated with nanoparticles have been greatly paid attention as nonvolatile memory devices of next generation due to their excellent transportation ability of charge carriers in the channel and outstanding capability of charge trapping in the floating gate. In this work, top-gate single ZnO nanowire-based FETs with and without Au nanoparticles were fabricated and their memory effects were characterized. Using thermal evaporation and rapid thermal annealing processes, Au nanoparticles were formed on an $Al_2O_3$ layer which was semi cylindrically coated on a single ZnO nanowire. The family of $I_{DS}-V_{GS}$ curves for the double sweep of the gate voltage at $V_{DS}$ = 1 V was obtained. The device decorated with nanoparticles shows giant hysterisis loops with ${\Delta}V_{th}$ = 2 V, indicating a significant charge storage effect. Note that the hysterisis loops are clockwise which result from the tunneling of the charge carriers from the nanowire into the nanoparticles. On the other hand, the device without nanoparticles shows a negligible countclockwise hysterisis loop which reveals that the influence of oxide trap charges or mobile ions is negligible. Therefore, the charge storage effect mainly comes from the nanoparticles decorated on the nanowire, which obviously demonstrates that the top-gate single ZnO nanowire-based FETs decorated with Au nanoparticles are the good candidate for the application in the nonvolatile memory devices of next generation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.255-255
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• 2009

In this work, nonvolatile nano-floating gate memory devices were fabricated with ZnO films and Al nanoparticles using the sputtering method on a glass substrate. Al nanoparticles acted as floating gate nodes in the devices. The fabricated device exhibits a threshold voltage shift of 1.7 V.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제37회 하계학술대회 초록집
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• pp.210-210
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• 2009

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 춘계학술대회 논문집
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• pp.86-89
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• 1995

In this pacer, The effect of the impedances in SNOSEFT s memory devices has been developed. The effect of source and drain impedances are measuring using the method of the field effect bias resistance in the inner resistance regions of the device structure and external bias resistance. The effect of impedance by source and drain resistance shows according to increasing to the storage of memory charges, shows according to a function of decreasing to the gate voltages, shows the delay of threshold voltages, The delay time of low conductance state and high conductance state by the impedance effect shows 3 [${\mu}$sec] and 1[${\mu}$sec] respectively.

• Transactions on Electrical and Electronic Materials
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• 제11권6호
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• pp.243-248
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• 2010

The emergence of different and disparate materials together with the convergence of both the 'old' and 'emerging' technologies is paving the way for integration of heterogeneous technologies that are likely to extend the limitations of silicon technology beyond the roadmap envisaged for complementary metal-oxide semiconductor. Formulation of new information processing concepts based on novel aspects of nano-scale based materials is the catalyst for new nanoarchitectures driven by a different perspective in realization of novel logic devices. The memory technology has been the pace setter for silicon scaling and thus far has pave the way for new architectures. This paper provides an overview of the inevitability of heterogeneous integration of technologies that are in their infancy through initiatives of material physicists, computational chemists, and bioengineers and explores the options in the spectrum of novel non-volatile memory technologies considered as forerunner of new logic devices.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 춘계학술대회 논문집
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• pp.91-96
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• 1992

The nonvolatile SNOSFET EEPROM memory devices with the channel width and iength of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] were fabricated by using the actual CMOS 1 [Mbit] process technology. The charateristics of I$\_$D/-V$\_$D/, I$\_$D/-V$\_$G/ were investigated and compared with the channel width and length. From the result of measuring the I$\_$D/-V$\_$D/ charges into the nitride layer by applying the gate voltage, these devices ere found to have a low conductance state with little drain current and a high conductance state with much drain current. It was shown that the devices of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$] represented the long channel characteristics and the devices of 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] represented the short channel characteristics. In the characteristics of I$\_$D/-V$\_$D/, the critical threshold voltages of the devices were V$\_$w/ = +34[V] at t$\_$w/ = 50[sec] in the low conductance state, and the memory window sizes wee 6.3[V], 7.4[V] and 3.4[V] at the channel width and length of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$], 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$], respectively. The positive logic conductive characteristics are suitable to the logic circuit designing.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.286-291
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• 2015

For highly scalable NAND flash memory applications, a compact ($4F^2/cell$) nonvolatile memory architecture is proposed and investigated via three-dimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

• 한국전기전자재료학회논문지
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• 제15권7호
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• pp.576-582
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• 2002

Nonvolatile semiconductor memory devices with reoxidized nitrided oxide(RONO) gate dielectrics were fabricated, and nitrogen distribution and bonding species which contribute to memory characteristics were analyzed. Also, memory characteristics of devices depending on the anneal temperatures were investigated. The devices were fabricated by retrograde twin well CMOS processes with $0.35\mu m$ design rule. The processes could be simple by in-situ process in growing dielectric. The nitrogen distribution and bonding states of gate dielectrics were investigated by Dynamic Secondary Ion Mass Spectrometry(D-SIMS), Time-of-Flight Secondary Ion Mass Spectrometry(ToF-SIMS), and X-ray Photoelectron Spectroscopy(XPS). As the nitridation temperature increased, nitrogen concentration increased linearly, and more time was required to form the same reoxidized layer thickness. ToF-SIMS results showed that SiON species were detected at the initial oxide interface which had formed after NO annealing and $Si_2NO$ species within the reoxidized layer formed after reoxidation. As the anneal temperatures increased, the device showed worse retention and degradation properties. It could be said that nitrogen concentration near initial interface is limited to a certain quantity, so the excess nitrogen is redistributed within reoxidized layer and contribute to electron trap generation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.17-20
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• 2001

Nonvolatile semiconductor memory devices with reoxidized nitrided oxide(RONO) gate dielectric were fabricated, and nitrogen distribution and bonding species which contributing memory characteristics were analyzed. Also, memory characteristics of devices according to anneal temperatures were investigated. The devices were fabricated by 0.35$\mu\textrm{m}$ retrograde twin well CMOS processes. The processes could be simple by in-situ process of nitridation anneal and reoxidation. The nitrogen distribution and bonding state of gate dielectric were investigated by Dynamic Secondary Ion Mass Spectrometry(D-SIMS), Time-of-Flight Secondary ton Mass Spectrometry(ToF-SIMS), and X-ray Photoelectron Spectroscopy(XPS). Nitrogen concentrations are proportional to nitridation anneal temperatures and the more time was required to form the same reoxidized layer thickness. ToF-SIMS results show that SiON species are detected at the initial oxide interface and Si$_2$NO species near the new Si-SiO$_2$ interface that formed after reoxidation. As the anneal temperatures increased, the device showed worse retention and degradation properties. These could be said that nitrogen concentration near initial interface is limited to a certain quantity, so excess nitrogen are redistributed near the Si-SiO$_2$ interface and contributed to electron trap generation.