• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.61-67
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• 2020

This paper is to propose a hybrid memory adaptor using next-generation nonvolatile memory devices such as phase-change memory to improve the performance limitations of OpenStack-based object storage systems. The proposed system aims to improve the performance of the account and container servers for object metadata management. For this, the proposed system consists of locality-based dynamic page buffer, write buffer, and nonvolatile memory modules. Experimental results show that the proposed system improves the hit rate by 5.5% compared to the conventional system.

• Journal of the Semiconductor & Display Technology
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• v.9 no.2
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• pp.67-72
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• 2010

Recently increasing application of flash memory in mobile and ubiquitous related devices is due to its non-volatility, fast response time, shock resistance and low power consumption. Following this trend, SSD(Solid State Disk) using multiple flash chips, instead of hard-drive based storage system, started to widely used for its advantageous features. However, flash memory based storage subsystem should resolve the performance bottleneck for writing in perspective of speed and lifetime according to its disadvantageous physical property. In order to provide tangible performance, solutions are studied in aspect of reclaiming of invalid regions by decreasing the number of erasures and distributing the erasures uniformly over the whole memory space as much as possible. In this paper, we study flash memory recycling algorithms with multiple management units and demonstrate that the proposed algorithm provides feasible performance. The proposed method utilizes the partitions of the memory space by utilizing threshold values and reconfigures the management units if necessary. The performance of the proposed policies is evaluated through a number of simulation based experiments.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.118-123
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• 2020

In this paper, the design method of asynchronous nonvolatile memory module that can efficiently process and store large amounts of data without loss when the power turned off is proposed and implemented. PSRAM, which takes advantage of DRAM and SRAM, was used for data processing, and NAND flash memory was used for data storage and backup. The problem of a lot of signal interference due to the characteristics of memory devices was solved through PCB design using high-density integration technology. In addition, a boost circuit using the super capacitor of 0.47F was designed to supply sufficient power to the system during the time to back up data when the power is off. As a result, an asynchronous nonvolatile memory module was designed and implemented that guarantees reliability and stability and can semi-permanently store data for about 10 years. The proposed method solved the problem of frequent data loss in industrial sites and presented the possibility of commercialization by providing convenience to users and managers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.7-8
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• 2008

The memory characteristics of charge trap flash (CTF) with $HfO_2$ charge trap layer were investigated. Especially, we focused on the effects of tunnel barrier engineering consisted of $SiO_2/Si_3N_4/SiO_2$ (ONO) stack or $Si_3N_4/SiO_2/Si_3N_4$ (NON) stack. The programming and erasing characteristics were significantly enhanced by using ONO or NON tunnel barrier. These improvement are due to the increase of tunneling current by using engineered tunnel barrier. As a result, the engineered tunnel barrier is a promising technique for non-volatile flash memory applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.46-50
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• 2008

The effect of physicochemical properties of solvents on the microstructure of polyvinyl carbazole (PVK) film for non-volatile polymer memory was investigated. For the solubilization of PVK molecules and the preparation of PVK films, four solvents with different physicochemical properties of the Hildebrand solubility parameter and vapor pressure were considered: chloroform, tetrahydrofuran (THF), 1,1,2,2-tetrachloroethane (TCE), and N,N-dimehtylformamide (DMF). The solubility of PVK molecules in the solvents was observed by ultravioletvisible spectroscopy. PVK molecules were observed to be more soluble in chloroform, with a low Hildebrand solubility parameter, than solvents with higher values. The aggregated size and micro-/nano-topographical properties of PVK films were characterized using optical and atomic force microscopes. The PVK film cast from chloroform exhibited enhanced surface roughness compared to that from TCE and DMF. It was also confirmed that the microstructure of PVK film has an effect on the performance of non-volatile polymer memory.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.106-111
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• 2023

The importance of load-to-use latency has been highlighted as state-of-the-art computing cores adopt deep pipelines and high clock frequencies. The cascaded cache was recently proposed to reduce the access cycle of the L1 cache by utilizing differences in latencies among banks of the cache structure. However, this study assumes the cache is comprised of SRAM, making it unsuitable for direct application to non-volatile memory-based systems. This paper proposes a novel mechanism and structure for lowering dynamic energy consumption. It inserts monitoring logic to keep track of swap operations and write counts. If the ratio of swap operations to total write counts surpasses a set threshold, the cache controller skips the swap of cache blocks, which leads to reducing write operations. To validate this approach, experiments are conducted on the non-volatile memory-based cascaded cache. The results show a reduction in write operations by an average of 16.7% with a negligible increase in latencies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.458-464
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• 2017

A magnetic tunnel junction (MTJ) based ternary content addressable memory (TCAM) is proposed which provides non-volatility. A unit cell of the TCAM has two MTJ's and 4.875 transistors, which allows the realization of TCAM in a small area. The equivalent resistance of parallel connected multiple unit cells is compared with the equivalent resistance of parallel connected multiple reference resistance, which provides the averaging effect of the variations of device characteristics. This averaging effect renders the proposed TCAM to be variation-tolerant. Using 65-nm CMOS model parameters, the operation of the proposed TCAM has been evaluated including the Monte-Carlo simulated variations of the device characteristics, the supply voltage variation, and the temperature variation. With the tunneling magnetoresistance ratio (TMR) of 1.5 and all the variations being included, the error probability of the search operation is found to be smaller than 0.033-%.

• Journal of Applied Reliability
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• v.10 no.1
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• pp.65-71
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• 2010

NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

• Journal of KIISE
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• v.42 no.4
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• pp.427-433
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• 2015

The rapid advancement of computing technology has triggered the need for fast data I/O processing and high-performance storage technology. Next generation memory technology, which we refer to as new memory, is anticipated to be used for high-performance storage as they have excellent characteristics as a storage device with non-volatility and latency close to DRAM. This research proposes NTL (New memory Translation layer) as a technology to make use of new memory as storage. With the addition of NTL, conventional I/O is served with existing mature disk-based file systems providing compatibility, while new memory I/O is serviced through the NTL to take advantage of the byte-addressability feature of new memory. In this paper, we describe the design of NTL and provide experiment measurement results that show that our design will bring performance benefits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.330-338
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• 2016

Phase change memory (PCM) has been studied as an emerging memory technology for last-level cache (LLC) due to its extremely low leakage. However, it consumes high levels of energy in updating cells and its write endurance is limited. To relieve the write pressure of LLC, we propose a delta value indicator (DVI) by employing a small cache which stores the difference between the value currently stored and the value newly loaded. Since the write energy consumption of the small cache is less than the LLC, the energy consumption is reduced by access to the small cache instead of the LLC. In addition, the lifetime of the LLC is further extended because the number of write accesses to the LLC is decreased. To this end, a delta value indicator and controlling circuits are inserted into the LLC. The simulation results show a 26.8% saving of dynamic energy consumption and a 31.7% lifetime extension compared to a state-of-the-art scheme for PCM.