• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.51-65
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• 2008

The article presents the recent research development in polymer ferroelectric non-volatile memory. A brief overview is given of the history of ferroelectric memory and device architectures based on inorganic ferroelectric materials. Particular emphasis is made on device elements such as metal/ferroelectric/metal type capacitor, metal-ferroelectric-insulator-semiconductor (MFIS) and ferroelectric field effect transistor (FeFET) with ferroelectric poly(vinylidene fluoride) (PVDF) and its copolymers with trifluoroethylene (TrFE). In addition, various material and process issues for realization of polymer ferroelectric non-volatile memory are discussed, including the control of crystal polymorphs, film thickness, crystallization and crystal orientation and the unconventional patterning techniques.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.514-523
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• 2017

In this paper, we propose Adaptive Writeback-aware Cache management (AWC) to prolong the lifetime of non-volatile main memory systems by reducing the number of writebacks. The last-level cache in AWC is partitioned into Least Recently Used (LRU) segment and LRU using Dirty block Precedence (DP-LRU) segment. The DP-LRU segment evicts clean blocks first for giving reuse opportunity to dirty blocks. AWC can also determine the efficient size of DP-LRU segment for reducing the number of writebacks according to memory access patterns of programs. In the performance evaluation, we showed that AWC reduced the number of writebacks up to 29% and 46%, and saved the energy of a main memory system up to 23% and 49% in a single-core and multi-core, respectively. AWC also reduced the runtime by 1.5% and 3.2% on average compared to previous cache managements for non-volatile main memory systems, in a single-core and a multi-core, respectively.

• Journal of Korea Multimedia Society
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• v.19 no.7
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• pp.1179-1187
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• 2016

Through the rapid development of latest hardware technology, high performance as well as miniaturized size is the essentials of embedded system to meet various requirements from the society. It raises possibilities of genuine realization of IoT environment whose size and battery must be considered. However, the limitation of battery persistency and capacity restricts the long battery life time for guaranteeing real-time system. To maximize battery life time, low power technology which lowers the power consumption should be highly required. Previous researches mostly highlighted improving one single type of memory to increase ones efficiency. In this paper, reversely, considering multiple memories to optimize whole memory system is the following step for the efficient low power embedded system. Regarding to that fact, this paper suggests the study of volatile memory, whose capacity is relatively smaller but much low-powered, and non-volatile memory, which do not consume any standby power to keep data, to maximize the efficiency of the system. By executing function in specific memories, non-volatile and volatile memory, the quantitative analysis of power consumption is progressed. In spite of the opportunity cost of all of theses extra works to locate function in volatile memory, higher efficiencies of both power and energy are clearly identified compared to operating single non-volatile memory.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.32-39
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• 2008

Tunnel oxide of non-volatile memory (NVM) devices would be very difficult to downscale if ten-year data retention were still needed. This requirement limits further improvement of device performance in terms of programming speed and operating voltages. Consequently, for low-power applications with Fowler-Nordheim programming such as NAND, program and erase voltages are essentially sustained at unacceptably high levels. A promising solution for tunnel oxide scaling is tunnel barrier engineering (TBE), which uses multiple dielectric stacks to enhance field-sensitivity. This allows for shorter writing/erasing times and/or lower operating voltages than single $SiO_2$ tunnel oxide without altering the ten-year data retention constraint. In this paper, two approaches for tunnel barrier engineering are compared: the crested barrier and variable oxide thickness. Key results of TBE and its applications for NVM are also addressed.

• Electrical & Electronic Materials
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• v.8 no.2
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• pp.237-241
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• 1995

반도체 사업의 영역을 어떻게 분류하느냐에 따라 다르겠으나, 우리나라가 메모리 분야에서는 세계의 선진회사와 어깨를 나란히 한다는 점에서 메모리분야와 비메모리분야를 분류해 보고, 특히 비메모리분야의 기술동향과 이 분야에서의 우리나라 반도체 업체들의 사업전개 방향에 대해 방향을 제시해 보고자 한다. 메모리는 국내업체가 세계시장의 30%이상을 공급하고 있고, 256메가디램등 메모리분야에서 최첨단 제품의 개발이 속속 발표되고 있다. 반면에 그의 반도체 (비메모리분야)의 경우는 세계시장의 수 퍼센트도 공급하지 못하는 실정으로 반도체의 75% 가량을 차지하는 이 시장의 진입을 위해 장단기 계획을 수립하여 적극적으로 추진해야 할 것이다. 이 논문에서는 반도체 기술의 현재 상황을 국내외로 비교검토하고 우리나라와 기업의 발전방향을 제시해 보고자 한다.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.112-117
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• 2020

NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.

• 한국컴퓨터산업교육학회:학술대회논문집
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• 2003.11a
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• pp.75-78
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• 2003

An ideal semiconductor memory technology would combine or unify the attractive features of these technologies without acquiring any of the unattractive features. Such a memory technology, Phase Change RAM is now being developed using the class of elements known as chalcogenides. It is expected that this technology will eventually allow chips that have SRAM speed, DRAM cost, and Flash power characteristics and non-volatility.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• Bulletin of the Korean Chemical Society
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• v.33 no.7
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• pp.2207-2212
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• 2012

Dimethylaluminum isopropoxide (DMAI, $(CH_3)_2AlO^iPr$) as a single precursor, which contains one aluminum and one oxygen atom, has been adopted to deposit non-stoichiometric aluminum oxide ($AlO_x$) films by low pressure metal organic chemical vapor deposition without an additional oxygen source. The atomic concentration of Al and O in the deposited $AlO_x$ film was measured to be Al:O = ~1:1.1 and any serious interfacial oxide layer between the film and Si substrate was not observed. Gaseous by-products monitored by quadruple mass spectrometry show that ${\beta}$-hydrogen elimination mechanism is mainly contributed to the $AlO_x$ CVD process of DMAI precursor. The current-voltage characteristics of the $AlO_x$ film in Au/$AlO_x$/Ir metalinsulator-metal (MIM) capacitor structure show high ON/OFF ratio larger than ${\sim}10^6$ with SET and RESET voltages of 2.7 and 0.8 V, respectively. Impedance spectra indicate that the switching and memory phenomena are based on the bulk-based origins, presumably the formation and rupture of filaments.

• Journal of Magnetics
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• v.7 no.3
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• pp.101-105
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• 2002

MRAM (Magnetoresistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. This paper is for testing the actual electrical parameters to adopt MRAM technology in the semiconductor based memory device. The discussed topics are an actual integration of MRAM core cell and its properties such as electrical tuning of MOS/MTJ for data sensing and control of magnetic switching for data writing. It will be also tested that limits of the MRAM technology for a high density memory.