• Journal of the Korean Society for Precision Engineering
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• v.13 no.6
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• pp.168-176
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• 1996

A diagnosis system which can monitor tool breakage and chipping in real time was developed using a DSP(Digital Signal Processor) board in face milling operation. AR modelling and band energy method were used to extract the feature of tool states from cutting force signals. Artificial neural network embedded on DSP board discriminates different patterns from features got after signal processing. The features extracted from AR modelling are more accurate for the malfunction of a process than those from band energy method, even though the computing speed of the former is slow. From the processed features, we can construct the real time diagnosis system which monitors malfunction by using a DSP board having a parallel processing capability.

• Magazine of the Korean Society of Agricultural Engineers
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• v.45 no.1
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• pp.102-114
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• 2003

The objectives of the paper are to evaluate cell based pollutant loadings for different storm events, to monitor the hydrology and water quality of the Baran HP#6 watershed, and to validate AGNPS with the field data. Simplification was made to AGNPS in estimating storm erosivity factors from a triangular rainfall distribution. GIS-AGNPS interface model consists of three subsystems; the input data processor based on a geographic information system. the models. and the post processor Land use patten at the tested watershed was classified from the Landsat TM data using the artificial neural network model that adopts an error back propagation algorithm. AGNPS model parameters were obtained from the GIS databases, and additional parameters calibrated with field data. It was then tested with ungauged conditions. The simulated runoff was reasonably in good agreement as compared with the observed data. And simulated water quality parameters appear to be reasonably comparable to the field data.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2363-2366
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• 1998

The intent of this paper is to describe a neural network structure called dynamic neural processor(DNP), and examine how it can be used in developing a learning scheme for computing robot inverse kinematic transformations. The architecture and learning algorithm of the proposed dynamic neural network structure, the DNP, are described. Computer simulations are provided to demonstrate the effectiveness of the proposed learning using the DNP.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.65-68
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• 1996

Robotic manipulators have become increasingly important in the field of flexible automation. High speed and high-precision trajectory tracking are indispensable capabilities for their versatile application. The need to meet demanding control requirement in increasingly complex dynamical control systems under significant uncertainties, leads toward design of intelligent manipulation robots. This paper presents a new approach to the design of neural control system using digital signal processors in order to improve the precision and robustness. The TMS32OC31 is used in implementing real time neural control to provide an enhanced motion control for robotic manipulators. In this control scheme, the networks introduced are neural nets with dynamic neurons, whose dynamics are distributed over all the, network nodes. The nets are trained by the distributed dynamic back propagation algorithm. The proposed neural network control scheme is simple in structure, fast in computation, and suitable for implementation of real-time, control. Performance of the neural controller is illustrated by simulation and experimental results for a SCARA robot.

• 제어로봇시스템학회:학술대회논문집
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• 1995.10a
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• pp.60-64
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• 1995

The conventional neural network models are a parody of biological neural structures, and have very slow learning. In order to emulate some dynamic functions, such as learning and adaption, and to better reflect the dynamics of biological neurons, M.M. Gupta and D.H. Rao have developed a 'dynamic neural model'(DNU). Proposed neural unit model is to introduce some dynamics to the neuron transfer function, such that the neuron activity depends on internal states. Integrating an dynamic elementry processor within the neuron allows the neuron to act dynamic response Numerical examples are presented for a model system. Those case studies showed that the proposed DNU is so useful in practical sense.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.10
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• pp.69-76
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• 1993

In this paper we propose a design of a digital neuron processor using the residue number system for efficient matrix.vector multiplication involved in neural processing. Since the residue number system needs no carry propagation for modulus operations, the neuron processor can perform multiplication considerably fast. We also propose a high speed algorithm for computing the sigmoid function using the specially designed look-up table. Our method can be implemented area-effectively using the current technology of digital VLSI and siumlation results positively demonstrate the feasibility of our method. The proposed method would expected to adopt for application field of digital neural network, because it could be realized to currently developed digital VLSI Technology.

• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.8
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• pp.746-753
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• 2001

In this paper, we review the basic concept of Evolvable Hardware first. And we examine genetic algorithm processor and hardware reconfiguration method and implementation. By considering complexity and performance of hardware at the same time, we design genetic algorithm processor using modularization and parallel processing method. And we design frame that has connection structure and logic block on FPGA, and embody reconfigurable hardware that do so that this frame may be reconstructed by RAM. Also we implemented ECANS that information processing system such as living creatures'brain using this hardware reconfiguration method. And we apply ECANS which is implemented using the concept of Evolvable Hardware to time-series prediction problem in order to verify the effectiveness.

• Journal of the Korean Institute of Intelligent Systems
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• v.13 no.3
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• pp.334-341
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• 2003

In this paper, we proposed a recurrent time delayed neural network(RTDNN) controller which compensate a output of neural network controller. Even if learn by neural network controller, it can occur an bad results from disturbance or load variations. So in order to adjust above case, we used the fuzzy compensator to get an expected results. And the weight of main neural network can be changed with the result of learning a inverse model neural network of plant, so a expected dynamic characteristics of plant can be got. As the results of simulation through the second order plant, we confirmed that the proposed recurrent time delayed neural network controller get a good response compare with a time delayed neural network(TDU) controller. We implemented the controller using the DSP processor and applied in a hydraulic servo system. And then we observed an experimental results.

• 전자공학회논문지 IE
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• v.44 no.3
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• pp.12-22
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• 2007

In this paper, we designed of the high speed digital neuron processor in order to digital neural networks. we designed of the MAC(Multiplier and Accumulator) operation unit used residue number system without carry propagation for the high speed operation. and we implemented sigmoid active function which make it difficult to design neuron processor. The Designed circuits are descripted by VHDL and synthesized by Compass tools. we designed of MAC operation unit and sigmoid processing unit are proved that it could run time 19.6 nsec on the simulation and decreased to hardware size about 50%, each order. Designed digital neuron processor can be implementation in parallel distributed processing system with desired real time processing, In this paper.

• The Journal of Information Technology
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• v.10 no.3
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• pp.33-45
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• 2007

Systolic Array Processor is used for designing the special purpose processor in Digital Signal Processing, Computer Graphics, Neural Network Applications etc., since it has the characteristic of parallelism, pipeline processing and architecture of regularity. But, in case of using general design method, it has intial waiting period as large as No. of PE-1. And if the connected system needs parallel and simultaneous outputs, processor has some problems of the performance, since it generates only one output at each clock in output state. So in this paper, one dimensional Systolic Array Processor that is designed according to the dependance of data and operations using the partitioned sub-matrix is proposed for the purpose of improving the performance. 1-D Systolic Array using 4 partitioned sub-matrix has efficient method in case of considering those two problems.