• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.1
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• pp.39-51
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• 1998

In this paper, we propose signaling procedures amon network elements for a connection rerouting method which can reduce inter-switch handoff processing delay reduces the delay in the connection re-routing by reserving VPI/VCIs for possible inter-switch handoff calls in advance. Additionally, we mathematically analyze the signaling procedures and then suggest solutions to the relations with cluser size, network topoloty, handoff-request rete and handoff delay. With simulation, the solutions are validated. From numerical examples, we concluded taht handoff delay, one of the handoff QoSs, can be satisfied by adjusting the cluster size and network topology according to the handoff -request rate of service area. With our proposed signaling and analytic methods, we concluded that the connection rerouting method using cluster-sectoring effectively reduces the delay of inter-switch handoff processing than dynamic connection rerouting method. Our solutions are useful in guaranteeing the requested handoff delay (especially, inter-switch handoff delay) when the connection rerouting method is applied to ATM-based wireless/wired integrated network.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 1997.11a
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• pp.147-161
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• 1997

In the future, the performance of B-lSDN offering the multimedia and a various service depends on the performance of switch that is the important factor consisting of network. Bufferless banyan network consisted of MIN(multistage interconnection network) selected for- the fabric of ATM switch and has a limitation of performance because of blocking. Input buffered banyan networks with FIFO(first-in first-out) buffering scheme for the reduction of blocking and the cell bypass queueing theory for the reduction of HOL(head of line) blocking were seperately compared of the performance of switch. Specially input buffered banyan networks were applied monotonic buffering scheme that was proposed. As a result of simulation, Buffered Banyan Network with cell bypass queueing theory showed better performance than FIFO type input buffered Banyan network. Monotonic increase buffering scheme showed better performance than Monotonic decrease buffering scheme.

• Journal of information and communication convergence engineering
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• v.5 no.1
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• pp.23-28
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• 2007

In this paper, we propose ATM switch structure including AAL type 2 switch which can efficiently transmit low-bit rate data, even if the network has many endpoints. We simulate the architecture of ATM switch fabric that is modeled in computer program and analyze the performance according to offered loads. ATM switch proposed in this paper can support cell switching for all types of AAL cells which consist of AAL type 1, AAL type 2, AAL type 3/4, and AAL type 5 cells. We propose two switch fabric methods; One supports the AAL type 2 cell processing per input port, the other global AAL type 2 cell processing for every input port. The simulation results show that the latter is superior to the former. But the former has a strong point for easy implementation and extensibility. The proposed ATM switch fabric architecture is applicable to mobile communication, narrow band services over ATM network.

• Journal of KIISE:Information Networking
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• v.32 no.2
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• pp.244-253
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• 2005

In this paper, a performance evaluation model of the switch router with the multiple-buffered crossbar switches is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the crossbar switch. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. The performance of the multiple-buffered crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on a network that uses the multiple buffered crossbar switches. Less than $2\%$ differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

• 한국초전도학회:학술대회논문집
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• v.13
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• pp.42-42
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• 2003

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.122-125
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• 1999

In this paper, we propose a new architecture of the Banyan switch for a high speed networking and the high speed parallel computer. The proposed switching network with a remodeled architecture is a newly modified Banyan network with eight input and output pots, respectively. We have analysed the maximum throughput of the revised switch. Our analyses has shown that under the uniform random traffic load, the FIFO discipline is limited to 70％. Therefore the result of the analyses shows that the results of the networking simulation with the new switch are feasible and if we adopt such as new architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased about 11% when we compare the switching system with the input buffer system. We have designed and verified the new switching system in VHDL.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.81-84
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• 2001

A signal path control switch has been designed and implemented with AT&T 0.5${\mu}{\textrm}{m}$ CMOS ORCA FPGA. This device controls the path of digital signals in SDH-based transmission system. The proposed switch is suitable for self-healing operation which protects against transmission network failure. The self-healing operation of the switch is effectively done by the reconfigurable information stored in the registers of the switch. This device consists of eight subparts such west-east transmitting parts, west-east receiving parts, add-drop control parts, AIS control Part, and CPU interface part. The device is capable to a ring network as well as a linear network.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.537-540
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• 2000

In this paper, we propose and design new architecture of the modified Banyan switch for a high speed networking and the high speed parallel computer. The proposed switching network with a remodeled architecture is a newly modified Banyan network with eight input and output ports. The switch scheme is that two packets may arrive on different inputs destined for the same output. We have analyzed the maximum throughput of the revised switch. The result of the analyses shows good agreement simulation and if we adopt such architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased about lloio when we compare the switching system with the input buffer system. We have designed and verified the switching system in VHDL.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.703-705
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• 2011

내부 네트워크의 IP관리를 위해 많은 네트워크 관리 방안 및 솔루션들이 기 구축되어 운영 중이고, 이를 위해 내부 네트워크에 연결된 모든 단말에 특정 Agent를 설치하여 IP를 관리하고 있어 단말(PC, IPT전화기 등)의 OS에 따른 기종별 Agent의 호환문제 및 단말에 기 설치 운영중인 응용프로그램과의 충돌문제가 발생한다. 본 연구에서는 이러한 네트워크 IP관리를 위해 Agent가 필요 없는 네트워크 관리 방식을 제안한다. 네트워크 Switch장비 Firmware의 포트차단 설정을 이용한 기법으로 Agent의 설치없이 Switch장비의 Firmware를 이용하여 네트워크의 접근제어가 가능함을 제안한다. 이를 위하여 인가되지 않은 IP를 Switch장비의 Firmware로 차단하여 네트워크의 접근제어가 가능함을 증명하였다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.3 no.4
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• pp.274-279
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• 2002

ATM packet switching technologies for the purpose of the B-ISDN service are focused on high performance which represents good qualities on throughput, packet loss, and packet delay. ATM switch designs on a class of parallel interconnection network have been researched. But these are based on the self-routing function of it. It leads to conflict with each other, and to lose the packets. Therefore, this paper proposes the method based on Sort-Banyan network should be adopted for optimal routing algorithm. It is difficult to expect good hardware complexity. For good performance, a switch design based on the development of new routing algorithm is required. For the design of switch network, the packet distributor and multiplane are proposed. They prevent each packet from blocking as being transmitted selectively by two step distributed decision algorithm. This switch will be proved to be a good performance switch network that internal blocking caused from self-routing function is removed. Also, it is expected to minimize the packet loss and decrease the packet delay according to packet transmission.