• Journal of Korea Multimedia Society
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• v.18 no.12
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• pp.1475-1482
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• 2015

In network routers, buffers are used to resolve congestion and reduce packet loss rate whenever congestion occurs at bottleneck link. Most of the existing methods to manage such buffers focus only on queue-length-based control as one loop which have some issues of low link utilization and system stability. In this paper, we propose a novel framework which exploits two-loop control method, e.g. queue-length and congestion window size, combined with optimal margin method to facilitate parameter choices. Simulation results in ns-2 demonstrate that bottleneck link performance can be improved with higher link utilization (85%) and shorter queue length (22%) than the current deployed scheme in commercial routers (RED and DropTail).

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2936-2938
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• 2005

The deployment of multicast communication services in the internet is expected to lead a stable packet transfer even in heavy traffic as in network system environment. The core based tree scheme among many multicast protocols is the most popular and suggested recently. However, CBT exhibit two major deficiencies such as traffic concentration or poor core placement problem. so, measuring the bottleneck link bandwidth along a path is important for understanding th performance of multicast. We propose not only a definition of CBT's core link state that Steady-State, Normal-State and Bottleneck State according to the estimation link speed rate, but also the changeover of multicast routing scheme for traffic overload. In addition, we introduce anycast routing tree, a efficient architecture for construst shard multicast trees.

• International Journal of Computer Science & Network Security
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• v.22 no.3
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• pp.292-302
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• 2022

The radar tomographic imaging is based on the Radar Cross-Section "RCS" of the materials of a shape under examination and investigation. The RCS varies as the conductivity and permittivity of a target, where the target has a different material profile than other background objects in a scene. In this research paper, we use Hierarchical Performance Modeling "HPM" and a framework developed earlier to determine/spot bottleneck(s) for pattern recognition of materials using a combination of the Single Layer Perceptron (SLP) technique and tomographic images in radar systems. HPM provides mathematical equations which create Objective Functions "OFs" to find an average performance metric such as throughput or response time. Herein, response time is used as the performance metric and during the estimation of it, bottlenecks are found with the help of OFs. The obtained results indicate that processing images consumes around 90% of the execution time.

• Journal of IKEEE
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• v.24 no.3
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• pp.685-690
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• 2020

We propose an efficient convolutional neural network with much lower computational complexity and higher accuracy based on MobileNet V2 for mobile or edge devices. The proposed network consists of bottleneck layers with larger expansion factors and adjusted number of channels, and excludes a few layers, and therefore, the computational complexity is reduced by half. The performance the proposed network is verified by measuring the accuracy and execution times by CPU and GPU using ImageNet100 dataset. In addition, the execution time on GPU depends on the CNN architecture.

• Journal of Internet Computing and Services
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• v.9 no.4
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• pp.61-68
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• 2008

Ethernet passive optical network (EPON) is the next-generation technology mitigating the bottleneck between high-capacity local area networks (LANs) and a backbone network. The bottleneck is aggrevated depending on burstiness and long range dependence (LRD) of traffic characteristics as well as amount of outgoing traffic from the high-capacity LANs. The proposed scheme decreases average packet delay for data upstreaming by considering such traffic characteristics to dynamically allocate bandwidth to multiple optical network units (ONUs). In addition, it can appropriately support delay-sensitive traffic such as constant bit ratio (CBR) traffic by making maximum cycle time fix regardless of the number of ONUs. The comprehensive simulation results indicate that the proposed scheme acheives up to 77% and 82% lower than previous schemes in terms of average packet delay and average queue size while it limits the maximum cycle time to twice of the basic cycle time.

• Journal of applied mathematics & informatics
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• v.8 no.3
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• pp.1035-1045
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• 2001

We present two decomposition approximations for the mean sojourn times in open single class queing networks. If there is a single bottleneck station, the approximations are asymptotically exact in both light and heavy traffic. When applied to a Jackson network or an M/G/1 queue, these approximations are exact for all values of the traffic intensity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.65-72
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• 2005

We can integrate more IP blocks on a silicon die as the development of fabrication technologies and EDA tools. Consequently, we can design complicated SoC architecture including multi-processors. However, most of existing SoC buses have bottleneck in on-chip communication because of shared bus architectures, which result in the performance degradation of systems. In most cases, the performance of a multi-processor system is determined by efficient on-chip communication and the well-balanced distribution of computation rather than the performance of the processors. We propose an efficient SoC Network Architecture(SNA) using crossbar routers which provide a solution to ensure enough communication bandwidth. The SNA can significantly reduce the bottleneck of on-chip communication by providing multi-channels for multi-masters. According to the proposed architecture, we design a model system for the SNA. The proposed architecture has a better efficiency by $40\%$ than the AMBA AHB according to a simulation result.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.449-449
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• 2000

Many researchers have studied architectures for non-Neumann's computers because of escaping its bottleneck. To avoid the bottleneck, a neuron-based computer has been developed. The computer has only neurons and their connections, which are constructed of the learning. But still it has information processing facilities, and at the same time, it is like as a simplified brain to make inference; it is called "neuron-computer". No instructions are considered in any neural network usually; however, to complete complex processing on restricted computing resources, the processing must be reduced to primitive actions. Therefore, we introduce the instructions to the neuron-computer, in which the most important function is implications. There is an implication represented by binary-operators, but general implications for multi-value or fuzzy logics can't be done. Therefore, we need to use Lukasiewicz' operator at least. We investigated a neuron-computer having instructions for general implications. If we use the computer, the effective inferences base on multi-value logic is executed rapidly in a small logical unit.

• Journal of Industrial Technology
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• v.24 no.B
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• pp.177-186
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• 2004

The main bottleneck for a VOD system is bandwidth of storage or network I/O due to the high bandwidth requirements and long-lived nature of digital video. Patching is one of the most efficient techniques to overcome the bottleneck of the VOD system through the use of multicast scheme. In this paper, we propose a new patching scheme, P2P proxy patching, for improving the typical patching technique by jointly using the proxy prefix caching scheme and the P2P proxy. In our proposed scheme, each client play a role in a proxy for multicasting a regular stream to other clients that request the same stream. Due the use of the P2P proxy and the prefix caching, the server bandwidth is required significantly less than that of the typical patching technique. In the performance study, we show that our patching scheme can reduce the server bandwidth requirements compared with the existing patching techniques.

• ETRI Journal
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• v.34 no.4
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• pp.553-563
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• 2012

Serial peripheral interface (SPI) has been identified as a bottleneck in many wireless sensing systems today. SPI is used almost universally as the physical connection between the microcontroller unit (MCU) and radios, storage devices, and many types of sensors. Virtually all wireless sensor nodes today perform up to twice as many bus transactions as necessary to transfer a given piece of data, as an MCU must serve as the bus master in all transactions. To eliminate this bottleneck, we propose the master-handoff protocol. After the MCU initiates reading from the source slave device and writing to the sink slave device, the MCU as a master becomes a slave, and either the source or the sink slave becomes the temporary master. Experiment results show that this master-handoff technique not only cuts the data transfer time in half, but, more importantly, also enables a superlinear energy reduction.