• Title/Summary/Keyword: Nano-Electronics

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Formation of nano-pattern on metal using femtosecond laser pulses (펨토초 레이저를 이용한 금속 나노패턴 형성 연구)

  • Choi, Sung-Chul;Lee, Yeung-Lak;Noh, Young-Chul;Lee, Jong-Min;Ko, Do-Kyeong;Lee, Jung-Hoon;Kim, Kang-Yoon;Kim, Chang-Jong;Lee, Ung-Sang;Heo, Myeong-Koo
    • Korean Journal of Optics and Photonics
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    • v.17 no.2
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    • pp.203-206
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    • 2006
  • Femtosecond laser-induced nano-patterning of an Al surface coated on a slide glass is reported in this paper. It was found that the period of the laser-induced nano-patterning was much dependent on the incident laser power and pulse number. Through finely adjusting the laser power and pulse number, uniform nano-patterns could be formed on the Al surface. It is based on the interference of the incident laser beam with some form of a surface scatted electromagnetic wave. It was also found that an Al oxide layer played an important role in forming the nano-patterning on the Al surface.

Characteristics of Schottky Diode and Schottky Barrier Metal-Oxide-Semiconductor Field-Effect Transistors

  • Jang, Moon-Gyu;Kim, Yark-Yeon;Jun, Myung-Sim;Lee, Seong-Jae
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.5 no.2
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    • pp.69-76
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    • 2005
  • Interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are determined as $1.5{\times}10^{13} traps/cm^2$, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by $N_2$ annealing. Based on the diode characteristics, various sizes of erbium- silicided/platinum-silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from 20 m to 35nm. The manufactured SB-MOSFETs show excellent drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are compatible with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.

Organic Thin-Film Transistors with Screen Printed Silver Source/Drain Electrodes

  • Kim, Sam-Soo;Kim, Min-Soo;Choi, Gyu-Seok;Kim, Heon-Gon;Kim, Yong-Bae;Lee, Dong-Gu;Roh, Jae-Seong
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08b
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    • pp.1305-1307
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    • 2007
  • We show that the electrical properties of organic thinfilm transistors(OTFTs) can be enhanced by controlling the morphology of interface between screen printed electrodes and gate dielectrics. Modified surface of the insulator layer($SiO_2$) affect on the interface energy of electrode on $SiO_2$ layer. Contact angle measurement and FT-IR spectrum shows that the interface is properly modified. OTFTs device with high efficiency has been realized through modification of interface layer.

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Effects of Mg Suppressor Layer on the InZnSnO Thin-Film Transistors

  • Song, Chang-Woo;Kim, Kyung-Hyun;Yang, Ji-Woong;Kim, Dae-Hwan;Choi, Yong-Jin;Hong, Chan-Hwa;Shin, Jae-Heon;Kwon, Hyuck-In;Song, Sang-Hun;Cheong, Woo-Seok
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.2
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    • pp.198-203
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    • 2016
  • We investigate the effects of magnesium (Mg) suppressor layer on the electrical performances and stabilities of amorphous indium-zinc-tin-oxide (a-ITZO) thin-film transistors (TFTs). Compared to the ITZO TFT without a Mg suppressor layer, the ITZO:Mg TFT exhibits slightly smaller field-effect mobility and much reduced subthreshold slope. The ITZO:Mg TFT shows improved electrical stabilities compared to the ITZO TFT under both positive-bias and negative-bias-illumination stresses. From the X-ray photoelectron spectroscopy O1s spectra with fitted curves for ITZO and ITZO:Mg films, we observe that Mg doping contributes to an enhancement of the oxygen bond without oxygen vacancy and a reduction of the oxygen bonds with oxygen vacancies. This result shows that the Mg can be an effective suppressor in a-ITZO TFTs.

The ink jet printing of high conductivity circuits on various substrates using polymer capped nano-particle silver

  • Edwards, Charles O.;Howarth, James;James, Anthony
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07a
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    • pp.814-816
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    • 2005
  • In this paper, we describe how specially developed polymer capped, nano-particle silver inks can be used to print circuitry for applications like displays, RFID antennas and "disposable electronics". The requirements of printing on temperature sensitive flexible substrates (such as polymer films and papers) that require low temperature curing is also discussed.

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Performance Evaluation of Nano-Lubricants at Refrigeration Oil (나노입자를 적용한 냉장고 압축기용 오일의 윤활특성 평가)

  • Lee, Kwang-Ho;Hwang, Yu-Jin;Kwon, Lae-Un;Lee, Jae-Keun;Kim, Seok-Ro;Kim, Sun-Wook
    • Proceedings of the SAREK Conference
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    • 2008.06a
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    • pp.184-188
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    • 2008
  • It has been recognized that friction coefficient decreased with decreasing viscosity of oil in lubrication. In general, the more viscosity decreases, the more wear rate increases due to decrease load carrying capacity. It has been proposed that nano particles in oil decrease friction coefficient and wear rate. The purpose of this study is to apply oil of lower viscosity that mix with nano particles at the compressor used in a refrigerator to decrease friction coefficient keeping Load carrying capacity. Mineral oil of 8 cSt were used and mixed with nano particle. Friction coefficient was evaluated by a disk-on-disk tester. As a result, friction coefficient of nano oil decreased by 90% in comparison with raw oil. These results lead us to the conclusion that nano oil is new plan to raise efficiency of the compressor.

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A Nano-structure Memory with SOI Edge Channel and A Nano Dot (SOI edge channel과 나노 점을 갖는 나노 구조의 기억소자)

  • 박근숙;한상연;신형철
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.12
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    • pp.48-52
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    • 1998
  • We fabricated the newly proposed nano structure memory with SOI edge channel and a nano dot. The width of the edge channel of this device, which uses the side wall as a channel and has a nano dot on this channel region, was determined by the thickness of the recessed top-silicon layer of SOI wafer. The size of side-wall nano dot was determined by the RIE etch and E-Beam lithography. The I$_{d}$-V$_{d}$, I$_{d}$-V$_{g}$ characteristics of the devices without nano dots and memory characteristics of the devices with nano dots were obtained, where the voltage scan was done between -20 V and 14 V and the threshold voltage shift was about 1 V.t 1 V.

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Improving the Thermal Stability of Ni-Silicide Using Ni-V On Boron Cluster Implantend Source/drain for Nano-Scale CMOSFETs

  • Li, Shi-Guang;Lee, Won-Jae;Zhang, Ying-Ying;Zhun, Zhong;Jung, Soon-Yen;Lee, Ga-Won;Wang, Jin-Suk;Lee, Hi-Deok
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.11a
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    • pp.3-4
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    • 2006
  • 본 논문에서는 nano-scale CMOSFET을 위해 Boron Cluster ($B_{18}H_{22}$)가 이온주입된 SOI 와 Bulk 기판들 이용하였으며 실리사이드의 열 안정성 개선을 위해 Ni-V을 증착한 것과 순수 Ni을 증착한 것을 비교 분석 하였다. 결과 SOI위에 Ni-V을 증착한 것이 제일 낮은 면 저항을 보여주었고 반대로 Bulk위에는 제일 높은 면 저항을 보여 주었다. 단면을 측정한 결과 SOI 위에 Ni-V을 증착한 동일 조건의 Ni보다 Silicide의 두께가 두껍게 형성된 것을 확인하였다.

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Thermal Stability Improvement of Ni-silicide Using Ni-Co alloy for Nano-Scale CMOSFET Technology (나노급 CMOSFET을 윈한 Ni-Co 합금을 이용한 Ni-silicide의 열안정성 개선)

  • Park, Kee-Young;Zhang, Ying-Ying;Jung, Soon-Yen;Li, Shi-Guang;Zhun, Zhong;Lee, Ga-Won;Wang, Jin-Suk;Lee, Hi-Deok
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.06a
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    • pp.27-28
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    • 2007
  • In this paper, Ni-Co alloy was used for improvement of thermal stability of Ni silicide. The proposed Ni/Ni-Co structure exhibited wide temperature window of rapid thermal process. Sheet resistance as well as cross-sectional profile showed stable characteristics in spite of high temperature annealing up to $700^{\circ}C$ for 30min. Therefore, the proposed Ni/Ni-Co structure is highly promising for highly thermal immune Ni silicide for nano-scale CMOSFET technology.

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Fabrication of 1-${\mu}m$ channel length OTFTs by microcontact printing

  • Shin, Hong-Sik;Baek, Kyu-Ha;Yun, Ho-Jin;Ham, Yong-Hyun;Park, Kun-Sik;Lee, Ga-Won;Lee, Hi-Deok;Wang, Jin-Suk;Lee, Ki-Jun;Do, Lee-Mi
    • 한국정보디스플레이학회:학술대회논문집
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    • 2009.10a
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    • pp.1118-1121
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    • 2009
  • We have fabricated inverted staggered pentacene Thin Film Transistor (TFT) with 1-${\mu}m$ channel length by micro contact printing (${\mu}$-CP) method. Patterning of micro-scale source/drain electrodes without etching was successfully achieved using silver nano particle ink, Polydimethylsiloxane (PDMS) stamp and FC-150 flip chip aligner-bonder. Sheet resistance of the printed Ag nano particle films were effectively reduced by two step annealing at $180^{\circ}C$.

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