• Title/Summary/Keyword: Nano-Electronics

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EXPERIMENTS FOR VALIDATING NUMERICAL ANALYSIS USING ADVANCED FLOW VISUALIZATION TECHNOLOGIES (첨단 유동가시화 기술을 이용한 수치해석 검증용 실험)

  • Lee, S.J.
    • 한국전산유체공학회:학술대회논문집
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    • 2008.03a
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    • pp.14-17
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    • 2008
  • Recently, several advanced flow visualization techniques such as Particle Image Velocimetry (PIV) including stereo PIV, holographic PIV, and dynamic PIV have been developed. These advanced techniques have strong potential as the experimental technology which can be used for verifying numerical simulation. In addition, there would be indispensable in solving complicated thermo-fluid flow problems not only in the industrial fields such as automotive, space, electronics, aero- and hydro-dynamics, steel, and information engineering, but also in the basic research fields of medical science, bio-medical engineering, environmental and energy engineering etc. Especially, NT Nano Technology) and BT (Bio Technology) strongly demand these advanced measurement techniques, because it is difficult for conventional methods to observe most complicated nano- and bio-fluidic phenomena. In this paper, the basic principle of these advanced visualization techniques and their practical applications which cannot be resolved by conventional methods, such as flow in automotive HVAC system, ship and propeller wake, three-dimensional flow measurement in micro-conduits, and flow around a circulating cylinder will be introduced.

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Control of Size, Morphology and Crystalline Phase of Nanoparticles Using $CO_2$ Laser Irradiation ($CO_2$ 레이저 조사를 이용한 나노 입자의 크기, 형상과 결정상의 제어)

  • Lee, Dong-Geun;Choi, Man-Soo
    • Proceedings of the KSME Conference
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    • 2000.11b
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    • pp.180-185
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    • 2000
  • Nano crystalline or non-crystalline particles have been widely used in various industrial area, such as ceramics, catalysis, electronics, metallurgy and optic device. In all applications, synthesizing the particles as small as possible and controlling the crystalline phase according to its purpose are necessary for the enhancement of processing performance. In some cases, non-agglomerated particles may be necessary for solving the packing problems. This motivates our attempt of controlling size, morphology, phase of nano titania and silica particles. If one can enhance sintering rate of small aggregates independently of collision rate, one may expect that original aggregates can be changed into volume equivalent spheres and thereby the decrease of collision frequency due to the change leads to much smaller rate of growth of the particles. This is the basic idea of our control strategy.

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Multi-scale analysis of polymeric materials using OCTA (OCTA 를 이용한 폴리머 재료의 다중 스케일 해석)

  • Kim, Jae-Hyun;Choi, Byung-Ik;Kim, Jung-Yup
    • Proceedings of the KSME Conference
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    • 2003.04a
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    • pp.1094-1099
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    • 2003
  • Nanometer-sized structures are being applied to many fields including micro/nano electronics, optoelectronics, quantum computing, biosensors, etc. Multi-scale analysis technology is required for designing the reliable nanometer-sized structures and predicting their mechanical, chemical and electronic behaviors. In this paper, some techniques for multi-scale analysis are reviewed and their applicability and limitation are discussed. Research activity of nano process analysis team in KIMM is outlined. Especially, we concentrate on OCTA of Nagoya University in Japan for the analysis of polymeric materials. Detailed structure of OCTA is described and some examples are presented.

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EXPERIMENTS FOR VALIDATING NUMERICAL ANALYSIS USING ADVANCED FLOW VISUALIZATION TECHNOLOGIES (첨단 유동가시화 기술을 이용한 수치해석 검증용 실험)

  • Lee, S.J.
    • 한국전산유체공학회:학술대회논문집
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    • 2008.10a
    • /
    • pp.14-17
    • /
    • 2008
  • Recently, several advanced flow visualization techniques such as Particle Image Velocimetry (PIV) including stereo PIV, holographic PIV, and dynamic PIV have been developed. These advanced techniques have strong potential as the experimental technology which can be used for verifying numerical simulation. In addition, there would be indispensable in solving complicated thermo-fluid flow problems not only in the industrial fields such as automotive, space, electronics, aero- and hydro-dynamics, steel, and information engineering, but also in the basic research fields of medical science, bio-medical engineering, environmental and energy engineering etc. Especially, NT (Nano Technology) and BT (Bio Technology) strongly demand these advanced measurement techniques, because it is difficult for conventional methods to observe most complicated nano- and bio-fluidic phenomena. In this paper, the basic principle of these advanced visualization techniques and their practical applications which cannot be resolved by conventional methods, such as flow in automotive HVAC system, ship and propeller wake, three-dimensional flow measurement in micro-conduits, and flow around a circulating cylinder will be introduced.

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Theoretical and Experimental Analysis of Back-Gated SOI MOSFETs and Back-Floating NVRAMs

  • Avci, Uygar;Kumar, Arvind;Tiwari, Sandip
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.1
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    • pp.18-26
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    • 2004
  • Back-gated silicon-on-insulator MOSFET -a threshold-voltage adjustable device-employs a constant back-gate potential to terminate source-drain electric fields and to provide carrier confinement in the channel. This suppresses shortchannel effects of nano-scale and of high drain biases, while allowing a means to threshold voltage control. We report here a theoretical analysis of this geometry to identify its natural length scales, and correlate the theoretical results with experimental device measurements. We also analyze experimental electrical characteristics for misaligned back-gate geometries to evaluate the influence on transport behavior from the device electrostatics due to the structure and position of the back-gate. The backgate structure also operates as a floating-gate nonvolatile memory (NVRAM) when the back-gate is floating. We summarize experimental and theoretical results that show the nano-scale scaling advantages of this structure over the traditional front floating-gate NVRAM.

Patterning of Super-hydrophobic Surface Treated Polyimide Film (초발수 기판의 친수 패터닝을 이용한 금속배선화)

  • Rha, Jong-Joo;Um, Dae-Yong;Lee, Gun-Hwan;Choi, Doo-Sun;Kim, Wan-Doo
    • Proceedings of the KSME Conference
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    • 2008.11a
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    • pp.1553-1555
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    • 2008
  • Super-hydrophobic treated Polyimide film was used as a flexible substrate for developing a new method of metallization. Hydrophilic patterns were fabricated by IN irradiation through shadow mask. Patterned super-hydrophobic substrate was dipped into a bath containing silver nano ink Silver ink was only coated on hydrophilic patterned area. Metal lines of $600{\mu}m$ pitch were fabricated successfully. However, their thickness was too thin to serve as interconnection. To overcome this problem, iterative dipping was conducted. After repeating five times, the thickness of silver metal lines were increased to over than $2{\mu}$. After heat treatment of silver lines, their resistivities were reduced to order of $30{\mu}{\Omega}$-cm the similar level of values reported in other literatures. So, a new method of metallization has high potential for application of RFID antenna and flexible electronics substrates.

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Design and Multi-scale Analysis of Micro Contact Printing (미세접촉인쇄기법의 설계와 다중스케일해석)

  • Kim, Jung-Yup;Kim, Jae-Hyun;Choi, Byung-Ik
    • Proceedings of the KSME Conference
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    • 2003.11a
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    • pp.1927-1931
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    • 2003
  • Nanometer-sized structures are being applied to many fields including micro/nano electronics, optoelectronics, quantum computing, biosensors, etc. Micro contact printing is one of the most promising methods for manufacturing the nanometer-sized structures. The crucial element for the micro contact printing is the nano-resolution printing technique using polymeric stamps. In this study, a multi-scale analysis scheme for simulating the micro contact printing process is proposed and some useful analysis results are presented. Using the slip-link model [1], the dependency of viscoelasticity on molecular weight of polymer stamp is predicted. Deformation behaviors of polymeric stamps are analyzed using finite element method based upon the predicted viscoelastic properties.

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Interfacial Microstructures between Ag Wiring Layers and Various Substrates (Ag 인쇄배선과 이종재료기판과의 접합계면)

  • Kim, Keun-Soo;Suganuma, Katsuaki;Huh, Seok-Hwan
    • Journal of Welding and Joining
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    • v.29 no.5
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    • pp.90-94
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    • 2011
  • Ag metallic particles from nano-scale to submicron-scale are combined with organic solvent to provide fine circuits and interconnection. Ink-jet printing with Ag nano particle inks demonstrated the potentials of the new printed electronics technology. The bonding at the interface between the Ag wiring layer and the various substrates is very important. In this study, the details of interfaces in Ag wiring are investigated primarily by microstructure observation. By adjusting the materials and sintering conditions, nicely formed interfaces between Ag wiring and Cu, Au or organic substrates are achieved. In contrast, transmission electron microscope (TEM) image clearly shows interface debonding between Ag wiring and Sn substrate. Sn oxides are formed on the surface of the Sn plating. The formation of these is a root cause of the interface debonding.

Simulation of nonoverlapped source/drain-to-gate Nano-CMOS for low leakage current (낮은 누설전류를 위한 소스/드레인-게이트 비중첩 Nano-CMOS구조 전산모사)

  • Song, Seung-Hyun;Lee, Kang-Sung;Jeong, Yoon-Ha
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.579-580
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    • 2006
  • Simple nonoverlapped source/drain-to-gate MOSFETs to suppress GIDL (gate-induced drain leakage) is simulated with SILVACO simulation tool. Changing spacer thickness for adjusting length of Drain to Gate nonoverlapped region, this simulation observes on/off characteristic of nonoverlapped source/drain-to-gate MOSFETs. Off current is dramatically decreased with S/D to gate nonoverlapped length increasing. The result shows that maximum on/off current ratio is achieved by adjusting nonoverlapped length.

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Design of a Charge Pump Circuit Using Level Shifter for LED Driver IC (LED 구동 IC를 위한 레벨 시프터 방식의 전하펌프 회로 설계)

  • Park, Won-Kyeong;Park, Yong-Su;Song, Han-Jung
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.26 no.1
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    • pp.13-17
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    • 2013
  • In this paper, we designed a charge pump circuit using level shifter for LED driver IC. The designed circuit makes the 15 V output voltage from the 5 V input in condition of 50 kHz switching frequency. The prototype chip which include the proposed charge pump circuit and its several internal sub-blocks such as oscillator, level shifter was fabricated using a 0.35 um 20 V BCD process technology. The size of the fabricated prototype chip is 2,350 um ${\times}$ 2,350 um. We examined performances of the fabricated chip and compared its measured results with SPICE simulation data.