• Journal of Industrial Convergence
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• v.17 no.4
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• pp.95-102
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• 2019

Universities need to contribute to the sustainable development of their communities, with a primary purpose of education and research. Recently, the Economic and Social Impact(ESI), a measure of sustainability of universities, has been emphasized, but there is a lack of research on this. Therefore, this study examined the ESI indicators of existing universities and introduced cases of ESI development applied to K-university. In this study, we reviewed the ESI literature, analyzed domestic and international cases, and conduct an analysis of economic effect. As a result, we developed ESI indicators that includes both supply and demand side effects, and proposed an ESI assessment method that distinguishes the influence of universities and their impact on the community. Therefore, it is meaningful that this is a case of how universities measured ESI and how to use it. Future research will require advancement of the university's ESI assessment methodology, development of multipliers appropriate for the university, and comprehensive ESI indexing.

• Journal of the Korea Society for Simulation
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• v.21 no.2
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• pp.11-17
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• 2012

The past combats depended often on a number of firepower and manpower. However, integrated decision support viewpoint from communications, surveillance, reconnaissance, intelligence and so forth in combats witnessed in the Gulf, the Middle East, and Afghanistan have changed the trends of combat. That is, the force multipliers which many support systems enhance the combat potential of the fighting forces significantly become big issues to win or not in that combat. According to changing recent combat trend, Lanchester's combat model is being challenged to develop keeping pace with the new trend. We approach this paper as mathematical modeling about how the effect of terrain affects in the combat. Terrain information is invisible, but it is necessary to consider for analysis of warfare. Additionally, tangible or intangible elements affecting to attrition coefficients are continuely reflected to the combat model from decision-makers, then it will be a model closer to the reality and very suggestive to the actual world.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.59-68
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• 2002

In this paper, we design the two-dimensional Discrete Wavelet Transform (2D DWT) filter that is widely used in various applications such as image compression because it has no blocking effects and relatively high compression rate. The filter that we used here is two-channel four-taps QMF(Quadrature Mirror Filter) Lattice filter with PR (Perfect Reconstruction) property. The proposed DWT architecture, with two consecutive inputs shows an efficient performance with a minimum of such hardware resources as multipliers, adders, and registers due to a simple scheduling. The proposed architecture was verified by the RTL simulation, and utilizes the hardware 100%. Our architecture shows a relatively high performance with a minimum hardware when compared with other approaches. An efficient memory mapping and address generation techniques are introduced and the fixed-point arithmetic analysis for minimizing the PSNR degradation due to quantization is discussed.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.75-81
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• 2015

This paper proposed the new eight-parallel MDC FFT processor using the eight-parallel MDC architecture and the efficient scheduling scheme. The proposed FFT processor supports the 256-point FFT based on the modified radix-$2^6$ FFT algorithm. The proposed scheduling scheme can reduce the number of complex multipliers from eight to six without increasing delay buffers and computation cycles. Moreover, the proposed FFT processor can be used in OFDM systems required high throughput and low hardware complexity. The proposed FFT processor has been designed and implemented with a 90nm CMOS technology. The experimental result shows that the area of the proposed FFT processor is $0.27mm^2$. Furthermore, the proposed eight-parallel MDC FFT processor can achieve the throughput rate up to 2.7 GSample/s at 388MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.3-9
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• 2015

Under the maximum transmit power constraint and the minimum rate constraint, we propose the optimal number of transmit antennas and transmit power which maximize energy-efficiency (EE) in multi-user multiple-input multiple-output (MIMO) downlink system with the maximal ratio transmission (MRT) precoding. Because the optimization problem for the instantaneous channel is difficult to solve, we use independence of individual channel, average channel gain and path loss to approximate the objective function. Since the approximated EE optimization problem is two-dimensional search problem, we find the optimal number of transmit antennas and transmit power using Lagrange multipliers and our proposed algorithm. Simulation results show that the number of transmit antennas and power obtained by proposed algorithm are almost identical to the value by the exhaustive search.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.29-35
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• 2017

This paper presents a high-throughput area-efficient mixed-radix fast Fourier transform (FFT) processor using the efficient scheduling schemes. The proposed FFT processor can support 64, 128, 256, and 512-point FFTs for orthogonal frequency division multiplexing (OFDM) systems, and can achieve a high throughput using mixed-radix algorithm and eight-parallel multipath delay commutator (MDC) architecture. This paper proposes new scheduling schemes to reduce the size of read-only memories (ROMs) and complex constant multipliers without increasing delay elements and computation cycles; thus, reducing the hardware complexity further. The proposed mixed-radix MDC FFT processor is designed and implemented using the Samsung 65nm complementary metal-oxide semiconductor (CMOS) technology. The experimental result shows that the area of the proposed FFT processor is 0.36 mm2. Furthermore, the proposed processor can achieve high throughput rates of up to 2.64 GSample/s at 330 MHz.

• Journal of Korea Multimedia Society
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• v.8 no.2
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• pp.201-210
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• 2005

This paper proposes a power efficient 2-dimensional DCT/IDCT architecture driven by input data to be processed. The architecture achieves low power by taking advantage of the typically large fraction of zero and small-valued input processing data in video and image data compression. In particular, it skips multiplication by zero and dynamically activates/deactivates required bit-slices of fine-grain bit partitioned adders within multipliers and accumulators using simple input ANDing and bit-slice MASKing. The processed results from 1-D DCT/IDCT do not have unnecessary sign extension bits (SEBs), which are used for further power reduction in matrix transposer. The results extracted by bit-level transition activity simulations indicate significant power reduction compared to conventional designs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.857-864
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• 2006

This paper describes a design of low-power/small-area arithmetic circuits which are vector processing unit powering nit, divider unit and square-root unit for mobile 3D graphic accelerator. To achieve area-efficient and low-power implementation that is an essential consideration for mobile environment, the fixed-point f[mat of 16.16 is adopted instead of conventional floating-point format. The vector processing unit is designed using redundant binary(RB) arithmetic. As a result, it can operate 30% faster and obtained gate count reduction of 10%, compared to the conventional methods which consist of four multipliers and three adders. The powering nit, divider unit and square-root nit are based on logarithm number system. The binary-to-logarithm converter is designed using combinational logic based on six-region approximation method. So, the powering mit, divider unit and square-root unit reduce gate count when compared with lookup table implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.3C
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• pp.175-182
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• 2011

This paper presents a novel eight-parallel 128/256-point mixed-radix multi-path delay commutator (MRMDC) FFT/IFFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed FFT architecture can provide a high throughput rate and low hardware complexity by using an eight-parallel data-path scheme, a modified mixed-radix multi-path delay commutator structure and an efficient scheduling scheme of complex multiplications. The efficient scheduling scheme can reduce the number of complex multipliers at the second stage from 88 to 40. The proposed FFT/IFFT processor has been designed and implemented with the 90nm CMOS technology. The proposed eight-parallel FFT/IFFT processor can provide a throughput rate of up to 27.5Gsample/s at 430MHz.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.2
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• pp.144-150
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• 1990

This paper describes radix-4 Fast Fourier Transform (FFT) Processor designed with the new twice perfect shuffle developed from a perfect shuffle used in radix-2 FFT algorithm. The FFT Processor consists of a butterfly arithmetic circuit, address generators for input, output and coefficient, input and output registers and controller. Also, it requires the external ROM for storage of coefficient and RAM for input and output. The butterfly circuit includes 12 bit-serial ($16{\times}8$) multipliers, adders, subtractors and delay shift registers. Operating on 25 MHz two phase clock, this processor can compute 256 point FFT in 6168 clocks, i.e. 247 us and provides flexibility by allowing the user to select any size among 4,16,64,and256points. Being fabricated with 2-um double metal CMOS process, it includes about 28000 transistors and 55 pads in $8.0{\times}8.2mm^2$area.