• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.12
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• pp.691-700
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• 1999

This paper proposes a novel switching strategy of 1Mvar STATCON using cascade multilevel H-bridge inverter(HBI) for FACTS application. To control the reactive power instantaneously, the d-q dynamic system model is described and analyzed. A single pulse pattern based on the SHEM(Selective Harmonic Elimination Method) technique is determined from the look-up table to reduce the line current harmonics and a rotating fundamental frequency switching scheme is presented to adjust the DC voltage of each inverter capacitor at the same value. So the voltage unbalance problem between separately DC bus voltage is improved by using the proposed switching scheme. As a result, the presented inverter configuration not only reduces the system complexity by eliminating the isolation at the AC input side transformer but also improves the dynamic response to the step change of reactive power.

• Journal of Electrical Engineering and Technology
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• v.11 no.4
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• pp.829-838
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• 2016

This paper focuses on the engineering trade-offs in designing capacitor voltage balancing schemes for modular multilevel converters (MMC) HVDC: regulation performance and switching loss. MMC is driven by the on/off switch operation of numerous submodules and the key design concern is balancing submodule capacitor voltages minimizing switching transition among submodules because it represents the voltage regulation performance and system loss. This paper first introduces the state-of-the-art MMC-HVDC submodule capacitor voltage balancing methods reported in the literatures and discusses the trade-offs in designing these methods for HVDC application. This paper further proposes a submodule capacitor balancing scheme exploiting a control signal to flexibly interchange between the on-state and the off-state submodules. The proposed scheme enables desired performance-based voltage regulation and avoids unnecessary switching transitions among submodules, consequently reducing the switching loss. The flexibility and controllability particularly fit in high-level MMC HVDC applications where the aforementioned design trade-offs become more crucial. Simulation studies for MMC HVDC are performed to demonstrate the validity and effectiveness of the proposed capacitor voltage balancing algorithm.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.10
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• pp.16-26
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• 2014

This paper proposes new 13-level inverter topology and DC/DC converter buck-boost structure topology for multilevel, compounding uni-directional and bi-directional switches, and proposes high-efficient multilevel inverter system in which the proposed two PCS(Power Conditioning System) was connected in series. In proposed multilevel inverter of forming a output 13-level phase voltage by using total 18 switching parts, Then bi-directional switch has a characteristic of reducing conduction loss and controlling the reactive power effectively by separating electrically from the neutral point. DC/DC converter for supplying in dependent 3 DC voltage to the proposed multi-level inverter generates 180-degree phase shifted PWM by the symmetrically combined structure of 2 buck-boost converter and twice switching frequency efficiency can be obtained, meanwhile, the converter can step up/down the output voltage and 20% output can be generated comparing the input voltage. This proposed system is verified with the simulation and laboratory test.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1504-1512
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• 2016

This paper presents a new single-phase asymmetrical cascaded multilevel DC-link inverter. The proposed inverter comprises two stages. The main stage of the inverter consists of multiple similar cells, each of which is a half-bridge inverter consisting of two switches and a single DC source. All cells are connected in a cascaded manner with a fixed neutral point. The DC source values are not made equal to increase the performance of the inverter. The second circuit is a folded cascaded H-bridge circuit operating at a line frequency. One of the main advantages of this proposed topology is that it is a modular type and can thus be extended to high stages without changing the configuration of the main stage circuit. Two control schemes, namely, low switching with selective harmonic elimination and sinusoidal pulse width modulation, are employed to validate the proposed topology. The detailed approach of each control scheme and switching pulses are discussed in detail. A 150W prototype of the proposed system is implemented in the laboratory to verify the validity of the proposed topology.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.225-227
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• 2008

This paper deals with the implementation on a Field Programmable Gate Array (FPGA) of PWM switching patterns for a voltage multilevel inverter. The reference data in main microcontroller is transmitted to the FPGA through 16 general purpose I/O ports. Herein, three-phase reference voltage signals are addressed by the last 2-bit (bit 15-14) and their data are assigned in remaining 14-bit, respectively. The carrier signals are created by 16-bit counter in up-down counting mode inside FPGA according to desirable topology. Each reference signal is compared with all carrier signals to generate corresponding PWM switching patterns for control of the multilevel inverter. Useful advantages of this scheme are easy implementation, simple software control and flexibility in adaptation to produce many PWM signals. Some simulations and experiments are carried out to validate the proposed method.

• Proceedings of the KIEE Conference
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• 2000.07e
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• pp.136-141
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• 2000

This paper proposes the novel control of a static synchronous compensator (STATCOM). This STATCOM system consists of cascade multilevel inverter which employs H-bridge inverter(HBI) The STATCOM system is modeled in the d-q transform matrix. This model is used to design a controller. The selective harmonic elimination method(SHEM) allows to keep the total harmonic distortion (THD) low in the output voltage. The switching method produces the staircase type waveform in cascade multilevel inverter. To balance the DC voltages in HBIs capacitor, the rotated switching scheme is newly proposed in this paper. The proposed control scheme is verified in the simulated results.

• Journal of Power Electronics
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• v.15 no.4
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• pp.964-973
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• 2015

This paper presents a simple approach for the selective harmonic elimination (SHE) of multilevel inverter based on the transistor-clamped H-bridge (TCHB) family. The SHE modulation is derived from the sinusoidal voltage-angle equal criteria corresponding to the optimized switching angles. The switching angles are computed offline by solving transcendental non-linear equations characterizing the harmonic contents using the Newton-Raphson method to produce an optimum stepped output. Simulation and experimental tests are conducted for verification of the analytical solutions. An Altera DE2 field-programmable gate array (FPGA) board is used as the digital controller device in order to verify the proposed SHE modulation in real-time applications. An analysis of the voltage total harmonic distortion (THD) has been obtained for multiple output voltage cases. In terms of the THD, the results showed that the higher the number of output levels, the lower the THD due to an increase number of harmonic orders being eliminated.

• Journal of Power Electronics
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• v.17 no.4
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• pp.914-922
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• 2017

Multilevel converters have attracted a lot of attention in recent years. The efficiency parameters of a multilevel converter such as the switching losses and total harmonic distortion (THD) mainly depend on the modulation strategy used to control the converter. Among all of the modulation techniques, the selective harmonic elimination (SHE) method is particularly suitable for high-power applications due to its low switching frequency and high quality output voltage. This paper proposes a new expression for the SHE problem in five-level converters. Based on this new expression, a simple analytical method is introduced to determine the feasible modulation index intervals and to calculate the exact value of the switching angles. For each selected harmonic, this method presents three-level or five-level waveforms according to the value of the modulation index. Furthermore, a flowchart is proposed for the real-time implementation of this analytical method, which can be performed by a simple processor and without the need of any lookup table. The performance of the proposed algorithm is evaluated with several simulation and experimental results for a single phase five-level diode-clamped inverter.

• Journal of Power Electronics
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• v.19 no.4
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• pp.907-921
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• 2019

This paper presents two advanced hybrid pulse-width modulation (PWM) strategies for multilevel inverters (MLIs) that provide both common-mode voltage (CMV) elimination and current ripple reduction. The first PWM utilizes sequences that apply one switching state at the double ends of a half-carrier cycle. The second PWM combines the advantages of the former and an existing four-state PWM. Analyses of the harmonic characteristics of the two groups of switching sequences based on a general switching voltage model are carried out, and algorithms to optimize the current ripple are proposed. These methods are simple and can be implemented online for general n-level inverters. Using a three-level NPC inverter and a five-level CHB inverter, good performances in terms of the root mean square current ripple are obtained with the proposed PWM schemes as indicated through improved harmonic distortion factors when compared to existing schemes in almost the entire region of the modulation index. This also leads to a significant reduction in the current total harmonic distortion. Simulation and experimental results are provided to verify the effectiveness of the proposed PWM methods.

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.711-721
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• 2018

This paper presents a single-phase asymmetric half-bridge cascaded multilevel inverter based series active power filter (SAPF) for harmonic voltage compensation. The effect of level number on performance of the proposed SAPF is examined in terms of total harmonic distortion (THD) and system efficiency. Besides, the relationship between the level number and the number of switching device are compared with the other multilevel inverter topologies used in APF applications. The paper is also aimed to demonstrate the capability of the SAPF for compensating harmonic voltages alone, without using a passive power filter (PPF). To obtain the required output voltage, a new switching algorithm is developed. The proposed SAPF with levels of 7, 15 and 31 is used in both simulation and experimental studies and the harmonic voltages of the load connected to the point of common coupling (PCC) is compensated under two different loading conditions. Furthermore, very high system efficiency values such as 98.74% and 96.84% are measured in the experimental studies and all THD values are brought into compliance with the IEEE-519 Standard. As a result, by increasing the level number of the inverter, lower THD values can be obtained even under high harmonic distortion levels while system efficiency almost remains the same.