• 전기학회논문지
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• 제64권2호
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• pp.232-239
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• 2015

Faced with unbalanced grid operation mode, the high voltage direct current (HVDC) based on voltage source converter (VSC) can be properly controlled by a dual current control scheme. For the modular multilevel converter (MMC) controlling the AC side current is able to limit the arm current which flows along the IGBT of submodule (SM) to rated current. However the limitation of the arm current results in leaving the control range of active power at MMC confined to below the rated capacity. As a result, limiting the arm current causes the problem that the DC side voltage of the HVDC can not be controlled to the reference value since MMC HVDC adjusts the DC side voltage through the active power. In this paper, we propose the algorithm adjusting the active powers of both MMCs to resolve the problem. The back-to-back MMC HVDC applying the algorithm is modeled by PSCAD/EMTDC to verify the algorithm.

• Journal of Power Electronics
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• 제17권1호
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• pp.106-114
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• 2017

In this paper, the Selective Harmonic Mitigation-PWM (SHM-PWM) method is used in single-phase and three-phase Cascaded H-Bridge (CHB) inverters in order to fulfill different power quality standards such as EN 50160, CIGRE WG 36-05, IEC 61000-3-6 and IEC 61000-2-12. Non-equal DC link voltages are used to increase the degrees of freedom for the proposed SHM-PWM technique. In addition, it will be shown that the obtained solutions become continuous and without sudden changes. As a result, the look-up tables can be significantly reduced. The proposed three-phase modulation method can mitigate up to the 50th harmonic from the output voltage, while each switch has just one switching in a fundamental period. In other words, the switching frequency of the power switches are limited to 50 Hz, which is the lowest switching frequency that can be achieved in the multilevel converters, when the optimal selective harmonic mitigation method is employed. In single-phase mode, the proposed method can successfully mitigate harmonics up to the 50th, where the switching frequency is 150 Hz. Finally, the validity of the proposed method is verified by simulations and experiments on a 9-level CHB inverter.

• Journal of Power Electronics
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• 제15권3호
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• pp.670-684
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• 2015

The hybrid cascaded multilevel inverter (HCMLI) is a popular converter topology that is being increasingly used in high power medium voltage drives. The intricacy of the control technique for a HCMLI increases with the number of levels and due to fluctuating dc voltages. This paper presents a novel offline quadrant search based space vector modulation technique to synthesize a sinusoidal output from a dispersed pattern of voltage vectors due to different voltages in the auxiliary unit. Such an investigation has never been reported in the literature and it is being attempted for the first time. The method suggested distributes the voltage vectors for a reduced total harmonic distortion at minimal computation. In addition, the proposed algorithm determines the maximum modulation index in the linear modulation range in order to synthesize a sinusoidal output for both normal and abnormal vector patterns. It is better suited for a wide range of practical applications. It is particularly well suited for renewable source fed inverters which utilize large capacitor banks to maintain the dc link, which are prone to such slow fluctuations. The proposed quadrant search space vector modulation technique is simulated using MATLAB/SIMULINK and implemented using a Nexys-2 Spartan-3E FPGA for a developed prototype.

• Journal of Power Electronics
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• 제17권3호
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• pp.664-673
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• 2017

With the development of multilevel converters, cascaded single-phase H-bridge rectifiers (CHBRs) has become widely adopted in high-voltage high-power applications. In this study, sequence pulse modulation (SPM) is proposed for CHBRs. SPM is designed to balance the dc-link voltage and maintain the smooth changes of switch states. In contrast to phase disposition modulation, SPM balances the dc-link voltage even after removing the load of one submodule. The operation principle of SPM is deduced, and the unbalance degree of SPM is analyzed. All the proposed approaches are experimentally verified through a prototype of a four-module (nine-level) CHBR. Conclusions are drawn in accordance with the results of SPM and its imbalance degree analysis.

• Journal of Power Electronics
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• 제12권3호
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• pp.509-517
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• 2012

This paper presents control strategies for cascaded H-bridge multilevel active power filters (APFs). A current loop controller is implemented using a proportional-resonant (PR) regulator, which achieves zero steady-state error at target frequencies. The power balancing mechanism for the dc-link capacitor voltages is analyzed and a voltage balancing controller is presented. To mitigate the picket-fence effect of the conventional FFT algorithm under asynchronous sampling conditions, the Hanning Windowed-FFT algorithm is proposed for reference current generation (RCG). This calculates the frequency, amplitude and phase of individual harmonic components accurately and as a result, selective harmonic compensation (SHC) is achieved. Simulation and experimental results are presented, which verify the validity and effectiveness of the devised control algorithms.

• Journal of Electrical Engineering and Technology
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• 제9권5호
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• pp.1746-1752
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• 2014

This paper presents an application of proportional-resonant (PR) current controllers in modular multilevel converter-high voltage direct current (MMC-HVDC) system under unbalanced voltage conditions. The ac currents are transformed and controlled in the stationary reference frame (${\alpha}{\beta}$-frame). Thus, the complex analysis of the positive and negative sequence components in the synchronous rotating reference frame (dq-frame) is not necessary. With this control method, the ac currents are kept balanced and the dc-link voltage is constant under the unbalanced voltage fault conditions. The simulation results based on a detailed PSCAD/EMTDC model confirm the effectiveness of the proposed control method.

• Journal of Power Electronics
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• 제17권1호
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• pp.242-252
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• 2017

This paper deals with the blocking of DC-fault current during DC cable short-circuit conditions in HVDC (High-Voltage DC) transmission systems utilizing Modular Multilevel Converters (MMCs), where a new SubModule (SM) topology circuit for the MMC is proposed. In this SM circuit, an additional Insulated-Gate Bipolar Translator (IGBT) is required to be connected at the output terminal of a conventional SM with a half-bridge structure, hereafter referred to as HBSM, where the anti-parallel diodes of additional IGBTs are used to block current from the grid to the DC-link side. Compared with the existing MMCs based on full-bridge (FB) SMs, the hybrid topologies of HBSM and FBSM, and the clamp-double SMs, the proposed topology offers a lower cost and lower power loss while the fault current blocking capability in the DC short-circuit conditions is still provided. The effectiveness of the proposed topology has been validated by simulation results obtained from a 300-kV 300-MW HVDC transmission system and experimental results from a down-scaled HVDC system in the laboratory.

• 조명전기설비학회논문지
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• 제27권12호
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• pp.133-140
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• 2013

Cascaded H-Bridge multi-level inverters can be implemented through the series connection of single-phase modular power bridges. In recent years, multi-level inverters are becoming increasingly popular for high power applications due to its improved harmonic profile and increased power ratings. This paper presents a control method for balancing the dc-link voltage and ride-through enhancement, a modified pulse width-modulation Compensation algorithm of cascaded H-bridge multi-level inverters. During an under-voltage protection mechanism, causing the system to shut down within a few milliseconds after a power interruption in the main input sources. When a power interruption occurs finish, if the system is a large inertia restarting the load a long time is required. This paper suggests modifications in the control algorithm in order to improve the sag ride-through performance of ac inverter. The new proposed strategy recommends maintaining the DC-link voltage constant at the nominal value during a sag period, experimental results are presented.

• Journal of Power Electronics
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• 제14권6호
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• pp.1119-1129
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• 2014

This study proposes a novel five-level three-phase hybrid-clamped converter composed of only six switches and one flying capacitor (FC) per phase. The capacitor-voltage-drift phenomenon of the converter under the classical sinusoidal pulse width modulation (SPWM) strategy is comprehensively analyzed. The average current, which flows into the FC, is a function of power factor and modulation index and does not remain at zero. Thus, a specific modulation strategy based on space vector modulation (SVM) is developed to balance the voltage of DC-link and FCs by injecting a common-mode voltage. This strategy applies the five-segment method to synthesize the voltage vector, such that switching losses are reduced while optional vector sequences are increased. The best vector sequence is then selected on the basis of the minimized cost function to suppress the divergence of the capacitor voltage. This study further proposes a startup method that charges the DC-link and FCs without any additional circuits. Simulation and experimental results verify the validity of the proposed converter, modulation strategy, and precharge method.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2020년도 전력전자학술대회
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• pp.253-254
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• 2020

High Voltage Direct Current (HVDC) 시스템은 고압 직류송전을 위한 시스템이다. 고압 직류 송전을 위해서는 전력변환기가 교류전력을 직류전력으로 변환해주어야 하는데, 최근에는 모듈형 멀티레벨 컨버터(Modular Multilevel Converter, MMC)가 많이 적용되고 있다. MMC는 다수의 서브모듈이 직렬로 구성되어 있으며 DC-link단에 대용량 커패시터가 없다. MMC의 심각한 사고 중에 하나는 DC측 전력케이블의 단락사고로 시스템에 따라서 수십 kA 정도의 사고전류가 AC측 CB(Circuit Breaker)가 열리기 전까지 수십 ms에서 수백 ms동안 흐른다. 만약 하프브릿지 회로의 서브모듈로 구성된 컨버터에 별도 보호장치가 없으면 단락전류는 서브모듈의 하단 다이오드를 통해서 흐르게 되어 소손되게 된다. 이를 방지하기 위해 단락전류를 바이패스(by-pass) 시키기 위한 별도의 사이리스터를 추가하는데 이 기기의 사양은 DC 단락 전류를 충분히 견딜 수 있어야 한다. 본 논문에서는 사이리스터의 서지 전류 내력을 평가하기 위해 사양을 분석하고 시뮬레이션과 실험을 통해서 검증하였다.