• IEIE Transactions on Smart Processing and Computing
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• v.4 no.6
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• pp.434-442
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• 2015

In this paper, we propose an integrated spatial and view scalable video codec based on high efficiency video coding (HEVC). The proposed video codec is developed based on similarity and uniqueness between the scalable extension and 3D multi-view extension of HEVC. To improve compression efficiency using the proposed scalable multi-view video codec, inter-layer and inter-view predictions are jointly employed by using high-level syntaxes that are defined to identify view and layer information. For the inter-view and inter-layer predictions, a decoded picture buffer (DPB) management algorithm is also proposed. The inter-view and inter-layer motion predictions are integrated into a consolidated prediction by harmonizing with the temporal motion prediction of HEVC. We found that the proposed scalable multi-view codec achieves bitrate reduction of 36.1%, 31.6% and 15.8% on the top of ${\times}2$, ${\times}1.5$ parallel scalable codec and parallel multi-view codec, respectively.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.5
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• pp.1597-1610
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• 2022

At present, the main method of high-speed train chassis detection is using computer vision technology to extract keypoints from two related chassis images firstly, then matching these keypoints to find the pixel-level correspondence between these two images, finally, detection and other steps are performed. The quality and accuracy of image matching are very important for subsequent defect detection. Current traditional matching methods are difficult to meet the actual requirements for the generalization of complex scenes such as weather, illumination, and seasonal changes. Therefore, it is of great significance to study the high-speed train image matching method based on deep learning. This paper establishes a high-speed train chassis image matching dataset, including random perspective changes and optical distortion, to simulate the changes in the actual working environment of the high-speed rail system as much as possible. This work designs a convolutional neural network to intensively extract keypoints, so as to alleviate the problems of current methods. With multi-level features, on the one hand, the network restores low-level details, thereby improving the localization accuracy of keypoints, on the other hand, the network can generate robust keypoint descriptors. Detailed experiments show the huge improvement of the proposed network over traditional methods.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.7
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• pp.859-866
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• 2010

In this study, microinjection molding process using the newly developed micromold system, namely modularized and sectioned micromold system (MSMS), has been carried out for a replication of multi-level microstructures. The present MSMS consisted of several micromold modules, each having cross-sectional microstructures on the top surface. The micromold modules were precisely fabricated by deep X-ray lithography and subsequent nickel electroforming. By assembling the micromold modules, an MSMS having multi-level microstructures, which could be used as a mold system in micromolding processes, was obtained. In this manner, polymeric multi-level microstructures, such as the triangular prism microstructures on a stepped surface, were successfully replicated by the microinjection molding process.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.5
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• pp.892-897
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• 2007

This paper presents the output filter design and the output characteristic analysis by cut-off frequency set up of the LCR filter on NPC multi-level inverter with trap-filter. The single-phase NPC three-level inverter operates at low switching frequency. The proposed LC trap filter is comprised of a conventional LCR output filter, by using LC trap filter the need for high damping resistor and low LC cut-off frequency is eliminated. Also. low damping resistor is increased the output filter system. The multilevel inverter system used NPC type inverter in proper system for high power application and controller is used DSP(TMS320C31). The effectiveness of proposed system confirmed the validity through SPICE simulation and experimental results.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.7
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• pp.311-315
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• 2002

Chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD), inter-level dielectric (ILD) layers of multi-layer interconnections. In this paper, we studied the characteristics of polishing pad, which can apply shallow trench isolation (STI)-CMP process for global planarization of multi-level interconnection structure. Also, we investigated the effects of different sets of polishing pad, such as soft and hard pad. As an experimental result, hard pad showed center-fast type, and soft pad showed edge-fast type. Totally, the defect level has shown little difference, however, the counts of scratch was detected less than 2 on JR111 pad. Through the above results, we can select optimum polishing pad, so we can expect the improvements of throughput and device yield.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.53 no.3
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• pp.116-121
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• 2004

This paper proposes a novel UPFC based on 3-level Half-bridge modules, isolated through single-phase multi-winding transformers. The dynamic performance of proposed system was analyzed by simulation with EMTDC, assuming that the UPFC is connected with the 138-kV transmission line of one-machine-infinite-bus power system. The proposed system can be directly connected to the transmission line without series injection transformers. It has flexibility in expanding the operation voltage by increasing the number of 3-level Half-bridge modules.

• Transactions on Electrical and Electronic Materials
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• v.5 no.4
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• pp.138-142
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• 2004

This paper presents the improved bum-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved through the bum-in process. Reliability problem is more significant in MCP that includes over two chips in a package, because the failure of one chip (SRAM) has a large influence on the yield and quality of the other chips - Flash Memory, DRAM, etc. Therefore, the quality of SRAM must be guaranteed. To improve the quality of SRAM, we applied the improved wafer level bum-in process using multi cells selection method in addition to the previously used methods. That method is effective in detecting special failure. Finally, with the composition of some kind of methods, we could achieve the high quality of SRAM in Multi Chip Package.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.3
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• pp.416-420
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• 2008

This paper proposes a new method to improve signal characteristics at branches frequently met in system-level routing. We also introduce the numerical formula which can estimate the time delay due to branches and the simple design guideline for system-level routing. Finally, we propose the routing method which can eliminate the signal reflection for the case of one driver and two receivers (multi-drop topology).

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.10
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• pp.1121-1232
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• 1990

A hierarchical neural network structure is described for robot PTP trajectory planning. In the first level, the multi-layered Perceptron neural network is used for the inverse kinematics with the back-propagation learning procedure. In the second level, a saccade generation model based joint trajectory planning model in proposed and analyzed with several features. Various simulations are performed to investigate the characteristics of the proposed neural networks.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.2
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• pp.99-105
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• 2014

This paper proposes the reliability improvement of H-Bridge Multi-level (HBM) inverter. This reliability can be implemented through modularization of power circuit, distribution of controller, duplication of controller and communication, and continuous operation method in case of power cell failure for driving medium-voltage & high-power induction motor. It is shown that the modularization and expansion characteristics of the HBM inverter are improved since the individual inverter modules operate more independently when using the proposed concept. Also the fault tolerance is increased by using power cell bypass. The proposed design and control methods are described in detail and the validity of the proposed system is verified experimentally in various industrial fields.