• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.258-273
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• 2011

This paper designs and implements a multi-view 3D video player system which is operated faster than existing video player systems. The structure for obtaining the near optimum speed in a multi-processor environment by parallelizing the component modules is proposed to process large volumes of multi-view image data at high speed. In order to use the concurrency of bottleneck, we designed image decoding, synthesis and rendering modules in a pipeline structure. For load balancing, the decoder module is divided into the unit of viewpoint, and the image synthesis module is geometrically divided based on synthesized images. As a result of this experiment, multi-view images were correctly synthesized and the 3D sense could be felt when watching the images on the multi-view autostereoscopic display. The proposed application processing structure could be used to process large volumes of multi-view image data at high speed, using the multi-processors to their maximum capacity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4A
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• pp.426-433
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• 2008

In this paper, we present a method to improve the performance of the four transmit antenna quasi-orthogonal space-time block code (STBC) in the coded system. For the four transmit antenna case, the quasi-orthogonal STBC consists of two symbol groups which are orthogonal to each other, but intra group symbols are not. In uncoded system with the matched filter detection, constellation rotation can improve the performance. However, in coded systems, its gain is absorbed by the coding gain especially for lower rate code. We propose an iterative decoding method to improve the performance of quasi-orthogonal codes in coded systems. With conventional quasi-orthogonal STBC detection, the joint ML detection can be improved by iterative processing between the demapper and the decoder. Simulation results shows that the performance improvement is about 2dB at 1% frame error rate.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.527-528
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• 2008

In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory decoder is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.6C
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• pp.547-553
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• 2010

In this paper, novel approximated closed-form expressions of the SER(Symbol Error Rate) and BER(Bit Error Rate) are presented for the multi-input multi-output space-time block coding(MIMO-STBC) system employing two transmit and N receive antenna(s) in Rayleigh fading channels. Assuming a zero-forcing equalizer and a single-symbol maximum-likelihood (ML) decoder, the formulas are derived for the SER and BER, and then their approximated counterparts are also derived. In the derivation of the approximated expressions, acurve-fitting model is adopted that can eliminate the integral operators in the exact expressions.

• Journal of Communications and Networks
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• v.8 no.3
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• pp.275-285
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• 2006

Suitable for multi-input multi-output (MIMO) communications, the joint beamforming space-time block coding (JBSTBC) scheme is proposed for high-speed downlink transmission. The major functionality of the scheme entails space-time block encoder and joint transmit and receive eigen-beamformer (EBF) incorporating with block-ordered layered decoder (BOLD), and its operating principle is described in this paper. Within these functionalities, the joint EBFs will be utilized for decorrelating fading channels to cause an enhancement in the spatial diversity gain. Furthermore, to fortify the capability of layered successive interference cancellation (LSIC) in block-ordered layered decoding process, this paper will develop a simple ad-hoc transmit power discrimination scheme (TPDS) based on a particular power discrimination function (PDF). To confirm the superior behavior of the proposed JBSTBC scheme employing ad-hoc TPDS, computer simulations will be conducted under various channel conditions with the provision of detailed mathematical derivations for clarifying its functionality.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.8
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• pp.4255-4269
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• 2019

This paper proposes an image generation method using a Multi Discriminator Generative Adversarial Net (MDGAN) as a next generation 2D game sprite creation technique. The proposed GAN is an Autoencoder-based model that receives three areas of information-color, shape, and animation, and combines them into new images. This model consists of two encoders that extract color and shape from each image, and a decoder that takes all the values of each encoder and generates an animated image. We also suggest an image processing technique during the learning process to remove the noise of the generated images. The resulting images show that 2D sprites in games can be generated by independently learning the three image attributes of shape, color, and animation. The proposed system can increase the productivity of massive 2D image modification work during the game development process. The experimental results demonstrate that our MDGAN can be used for 2D image sprite generation and modification work with little manual cost.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.121-126
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• 2007

This paper describes a 9.09 Gb/s CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with Samsung $0.35{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the post layout simulation. The demultiplexer is achieved the maximum data rate of 9.09 Gb/s and the average power consumption of 69.93 mW. This circuit is expected to operate at higher speed than 9.09 Gb/s in the deep-submicron process of the high operating frequency.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.1
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• pp.1-9
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• 2014

This paper proposes a low-latency Sample Adaptive Offset filter (SAO) architecture and its Single Instruction Multiple Data (SIMD) optimization scheme to achieve fast High Efficiency Video Coding (HEVC) decoding in a multi-core environment. According to the HEVC standard and its Test Model (HM), SAO operation is performed only at the picture level. Most realtime decoders, however, execute their sub-modules on a Coding Tree Unit (CTU) basis to reduce the latency and memory bandwidth. The proposed low-latency SAO architecture has the following advantages over picture-based SAO: 1) significantly less memory requirements, and 2) low-latency property enabling efficient pipelined multi-core decoding. In addition, SIMD optimization of SAO filtering can reduce the SAO filtering time significantly. The simulation results showed that the proposed low-latency SAO architecture with significantly less memory usage, produces a similar decoding time as a picture-based SAO in single-core decoding. Furthermore, the SIMD optimization scheme reduces the SAO filtering time by approximately 509% and increases the total decoding speed by approximately 7% compared to the existing look-up table approach of HM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.982-989
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• 2007

In this paper, we propose a 3DTV system that considers user's view point and display environment. The proposed system consists of 3 parts - multi-view encoder/decoder, face-tracker, and 2D/3D converter. The proposed system try to encode multi-view sequence and decode it in accordance with the user's view point and it also gives a stereopsis to the multi-view image by using of 2D/3D conversion which converts decoded two-dimensional(2D) image to three-dimensional(3D) image. Experimental results shows that we are able to correctly reconstruct a stereoscopic view that is exactly corresponding to user's view point.

• Journal of IKEEE
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• v.24 no.1
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• pp.186-193
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• 2020

In this paper, we propose a multi-threading system to support reconfigurable hardware accelerators on Zynq SoC. We implement high-performance JPEG decoder with reconfigurable 2D IDCT hardware accelerators to achieve maximum performance available on the platform. In this system, up to four reconfigurable hardware accelerators synchronized with SW threads can be dynamically reconfigured to provide adaptive computing capabilities according to the given image resolution and the compression ratio. JPEG decoding is operated using images with resolutions 480p, 720p, 1080p at the compression ratio of 7:1-109:1. We show that significant performance improvements are achieved as the image resolution or the compression ratio increase. For 1080p resolution, the performance improvement is up to 79.11 times with throughput speed of 99 fps at the compression ratio 17:1.