• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 전력전자학술대회 논문집
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• pp.129-130
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• 2016

본 논문에서는 근사 계단 제어 변조(Nearest Level Control Modulation)로 동작하는 모듈형 멀티레벨 컨버터(Modular Multi level Converter)에서 충전 회로나 반송파(Carrier)없이 초기 충전(Pre-charging)하는 새로운 방식을 제안하였다. 이의 성능을 검증하기 위해 PSCAD/EMTDC 소프트웨어를 통해 암(Arm)당 12개의 서브모듈(Sub-Module)로 구성된 3상 10kVA 모듈형 멀티레벨 컨버터를 구현 및 시뮬레이션을 수행하였다.

• Journal of the Optical Society of Korea
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• 제16권2호
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• pp.107-114
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• 2012

In this paper, we propose a new modulation scheme called multi-coded variable pulse position modulation (MC-VPPM) for visible light communication systems. Two groups of signals (Pulse Width Modulation (PWM) and Pulse Position Modulation (PPM) groups) are multi-coded by orthogonal codes for transmitting data simultaneously. Then, each multi-level value of the multi-coded signal is converted to pulse width and position which results in not only an improved data rate, but also a processing gain in reception. In addition, we introduce average duty ratio and cyclic shift concepts in PWM through which dimming control for light illumination can be supported without any degradation in communication performance. Through simulation, we confirm that the proposed MC-VPPM shows a comparable BER curve and much greater achievable data rate than the conventional VPPM scheme using a visible light optical channel environment.

• Journal of the Optical Society of Korea
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• 제20권1호
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• pp.29-35
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• 2016

This paper deals with a design method and capacity loss of an efficient multi-level modulation scheme for dimmable visible light communications (VLC) systems that use light-emitting diodes (LEDs) with efficiency droop. To this end, the impact of such an impairment on dimmable VLC is addressed with respect to multi-level modulations based on pulse-amplitude modulation (PAM) via data-rate optimization formulation.

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.489-500
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• 2014

This paper presents a simple modified unipolar carrier-based pulsewidth modulation (CB-PWM) strategy for the three-level neutral-point-clamped (NPC) voltage source inverter (VSI). Analytical expressions for the relationship between modulation reference signals and output voltages are derived. The proposed modulation technique for the three-level NPC VSI includes the maximum and minimum of the three-phase sinusoidal reference voltages with zero-sequence voltage injection concept. The proposed modified CB-PWM strategy incorporates a novel method that requires only of one triangular carrier wave for generate the gating pulses in three-level NPC VSI. It has the advantages of being simplifying the algorithm with no need of complex two/multi-carrier pulsewidth modulation or space vector modulation (SVM) and it's also simple to implement. The possibility of the proposed CB-PWM technique has been verified though computer simulation and experimental results.

• 한국통신학회논문지
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• 제40권9호
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• pp.1667-1671
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• 2015

멀티레벨 홀로그래픽 데이터 저장장치는 한 픽셀에 1비트 이상의 데이터 저장이 가능하여 한정된 공간에서 저장 밀도를 높일 수 있기 때문에 차세대 대용량 저장장치로 부각되고 있다. 한편 레벨의 증가는 동일한 픽셀개수에서 코드워드의 수를 증가시킬 수 있기 때문에 적절히 코드워드를 선택하면 변조부호의 최소거리를 증가시킬 수 있다. 최소거리의 증가는 노이즈 마진이 증가하므로 변조부호의 오류 정정 능력이 향상된다. 본 논문에서는 부호율이 1인 세 가지 변조부호를 제안하고, 이들의 최소거리에 따른 성능을 비교한다. 레벨의 증가로 코드워드간의 최소거리를 증가시켜 노이즈 마진을 증가시켰지만, 픽셀의 레벨이 증가할수록 문턱값 검출이 어렵기 때문에 낮은 레벨에 대한 변조부호가 더 좋은 성능을 보였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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• pp.159-164
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• 1998

This paper proposes a SVPWM (space vector pulse width modulation) strategy for a multi-level voltage source inverter. This strategy is easily implemented as SPWM (sinusoidal pulse width modulation) and has the same DC-link voltage utilization as general SVPWM. The method to keep the voltage balancing of DC-link also is proposed by the analysis model of DC-link voltage fluctuation. The usefulness of the proposed SVPWM is verified through the simulation.

• 전기학회논문지
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• 제65권10호
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• pp.1655-1663
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• 2016

Recently the researches on Modular Multi-level Converter (MMC) are being highlighted because high quality and efficient power transmission are key issues in the High Voltage Direct Current (HVDC) transmission system. This paper proposes an improved pre-charging method for the sub-module capacitors in MMC that operates in Nearest Level Control (NLC) modulation. The proposed method does not require additional circuits or Pulse Width Modulation (PWM) techniques. The feasibility of proposed method was verified through computer simulations for a scaled 3-phase 10kVA MMC with 12 sub-modules per each arm. Hardware experiments with a scaled prototype were performed in the lab to confirm the simulation results.

• 전력전자학회논문지
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• 제15권4호
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• pp.288-295
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• 2010

멀티레벨 인버터는 대용량 전력변환 분야의 요구를 만족하면서 파형왜곡을 감소시켜 전력품질 향상시킬 수 있으므로 근래에 상당히 주목받고 있다. 그런데 전압레벨이 증가함에 따라 복잡한 PWM 알고리즘을 구현하는데 FPGA가 적합하다. 본 논문에서는 FPGA로 5-레벨 다이오드 클램핑형 멀티레벨 인버터의 PWM 신호발생 기법을 제시한다. 유도전동기 제어용 DSP와 FPGA사이에 3상 기준전압 값을 안정되게 전송하는 기법을 제시한다. 32-비트 DSP와 cyclone-III FPGA를 사용한 실험 및 시뮬레이션을 통하여 반송신호 발생 방법으로 PWM 신호를 발생시키는 기법의 타당성을 검증한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

• 한국마린엔지니어링학회:학술대회논문집
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• 한국마린엔지니어링학회 2005년도 전기학술대회논문집
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• pp.1022-1028
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• 2005

This paper is presented the analysis results and simulation results of cascaded H-bridge 7 level inverter with various modulation index. Stepped waveform having number of switching was used to eliminate harmonic components. Switching angles according to modulation index are calculated numerically. Therefore, 3 times of switching with 7 level topology and QWS(Quarter Wave Symmetry) could eliminate 5th and 7th harmonics. The harmonic characteristics are compared to those of space vector modulation method which known as common modulation method in industrial field. Stepped waveform method showed higher ability to reduce, especially lower order of harmonics.