• International Journal of Computer Science & Network Security
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• v.23 no.10
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• pp.1-10
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• 2023

This paper proposes a method to extend Inter-Carrier Interference (ICI) canceling Orthogonal Frequency Division Multiplexing (OFDM) receivers for 5G mobile systems to spatial multiplexing 2×2 MIMO (Multiple Input Multiple Output) systems to support high-speed ground transportation services by linear motor cars traveling at 500 km/h. In Japan, linear-motor high-speed ground transportation service is scheduled to begin in 2027. To expand the coverage area of base stations, 5G mobile systems in high-speed moving trains will have multiple base station antennas transmitting the same downlink (DL) signal, forming an expanded cell size along the train rails. 5G terminals in a fast-moving train can cause the forward and backward antenna signals to be Doppler-shifted in opposite directions, so the receiver in the train may have trouble estimating the exact channel transfer function (CTF) for demodulation. A receiver in such high-speed train sees the transmission channel which is composed of multiple Doppler-shifted propagation paths. Then, a loss of sub-carrier orthogonality due to Doppler-spread channels causes ICI. The ICI Canceller is realized by the following three steps. First, using the Demodulation Reference Symbol (DMRS) pilot signals, it analyzes three parameters such as attenuation, relative delay, and Doppler-shift of each multi-path component. Secondly, based on the sets of three parameters, Channel Transfer Function (CTF) of sender sub-carrier number n to receiver sub-carrier number l is generated. In case of n≠l, the CTF corresponds to ICI factor. Thirdly, since ICI factor is obtained, by applying ICI reverse operation by Multi-Tap Equalizer, ICI canceling can be realized. ICI canceling performance has been simulated assuming severe channel condition such as 500 km/h, 8 path reverse Doppler Shift for QPSK, 16QAM, 64QAM and 256QAM modulations. In particular, 2×2MIMO QPSK and 16QAM modulation schemes, BER (Bit Error Rate) improvement was observed when the number of taps in the multi-tap equalizer was set to 31 or more taps, at a moving speed of 500 km/h and in an 8-pass reverse doppler shift environment.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.2
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• pp.97-102
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• 2010

In this paper, an area-efficient FFT processor is proposed for IEEE 802.16e mobile WiMax systems. The proposed scalable FFT processor can support the variable length of 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput. The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 16% and 27%, respectively, compared with those of the 4-channel radix-2 MDC (R2MDC) FFT processor.