• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.90-93
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• 2002

In this work, an efficient lifting implementation of invertible deinterlacing is proposed. The invertible deinterlacing is a technique developed for intra-frame-based video coding as a preprocessing. Unlike the conventional deinterlacing, it preserves the sampling density and has the invertibility. For a special selection of filters, it is shown that the deinterlacing can be implemented efficiently by an in-place computation. It is also shown that the deinterlacing can be combined with the lifting discrete wavelet transform (BWT) employed in JPEG2000. A bit modification of the original lifting DWT is shown to provide the simultaneous implementation of deinterlacing. This fact makes the proposed technique attractive for the application to Motion-JPEG2000. The inverse transform and the reversible lifting implementation are also discussed.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.417-420
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• 2000

In this paper, the design and the implementation of a realtime monitoring system using WWW protocol over the Internet is described. The overall system architecture and the functional structure of the system are presented. A Java applet is used in the development of the system for the motion picture effect of JPEG still images. The system is tested on a LAN and the experimental results are described.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.75-84
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• 2004

In this paper, we proposed an efficient hardware architecture of line-based lifting algorithm for Motion JPEG2000. We proposed a new architecture of a lifting-based filtering cell which has an optimized and simplified structure. It was implemented in a hardware accommodating both (9,7) and (5,4) filter. Since the output rate is linearly proportional to the input rate, one can obtain the high throughput through parallel operation simply by adding the hardware units. It was implemented into both of ASIC and FPGA The 0.35${\mu}{\textrm}{m}$ CMOS library from Samsung was used for ASIC and Altera was the target for FRGA. In ASIC, the proposed architecture used 41,592 gates for the lifting arithmetic and 128 Kbit memory. For FPGA it used 6,520 LEs(Logic Elements) and 128 ESBs(Embedded System Blocks). The implementations were stably operated in the clock frequency of 128MHz and 52MHz, respectively.

• Proceedings of the KSME Conference
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• 2000.04b
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• pp.655-660
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• 2000

Animation technique from the PIV database is particularly emphasized to give macroscopic and quantitative description of complex flow fields. This paper shows animation construction and application example for the post-processing of PIV data. As examples, first case is a pitching airfoil immersed in tree surface water circulating tunnel. Second case is a wake of a model-ship. Third case of PIV data is a large scale surface flow field. Obtained images are processed in time sequence by PIV exclusive routines where an efficient and reliable cross correlation algorithm is included for vector identification. All. animation Jobs are implemented completely on single personal computer environment. Compressed digital images are obtained initially by Motion-JPEG board and various An files are finally obtained through graphic processes.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.45-45
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• 2000

This paper proposes a remote control system that combines computer network and an autonomous mobile robot. We control remotely an autonomous mobile robot with vision via the internet to guide it under unknown environments in the real time. The main feature of this system is that local operators need a World Wide Web browser and a computer connected to the internet communication network and so they can command the robot in a remote location through our Home Page. The hardware architecture of this system consists of an autonomous mobile robot, workstation, and local computers. The software architecture of this system includes the server part for communication between user and robot and the client part for the user interface and a robot control system. The server and client parts are developed using Java language which is suitable to internet application and supports multi-platform. Furthermore, this system offers an image compression method using motion JPEG concept which reduces large time delay that occurs in network during image transmission.

• Journal of Broadcast Engineering
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• v.9 no.2
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• pp.119-130
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• 2004

We have developed a prototype super-high-definition (SHD) digital cinema distribution system that can store, transmit, and display eight-million-pixel motion pictures that have the image quality of a 35-mm film movie. The system contains a movie server, a real-time decoder, and an SHB projector. Using a Gigabit Ethernet link and TCP/IP, the server transmits JPEG2000 compressed motion picture data streams to the decoder at transmission speeds as high as 300 Mbps. The received data streams are decompressed by the decoder, and then projected onto a screen via the projector. By using an enlarged TCP window, multiple TCP streams, and a shaping function to control the data transmission quantity, we achieved real-time streaming of SHD movie data at about 300 Mbps between Chicago and Los Angeles, a distance of more than 3000 km. We also improved the decoder performance to show movies with Image qualities of 450 Mbps or higher. Since UDP is more suitable than TCP for fast long-distance streaming, we have developed an SHD digital cinema UDP relay system, in which UDP is used for transmission over a fast long-distance network. By using four pairs of server-side-proxy and decoder-side-proxy, 450-Mbps movie data streams could be transmitted.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1113-1124
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel fur the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter. The implemented H/W used the 69%(16980) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation of 60 fields/sec(30 frames/sec).