• The Transactions of the Korean Institute of Electrical Engineers A
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• v.54 no.7
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• pp.323-327
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• 2005

This paper presents an operator training simulator for power system restoration against massive black-out. The system is designed especially focused on the generality and convenient setting up for initial condition of simulation. The former is accomplished by using power flow calculation methodology, and PSS/E data is used to define the initial situation. The proposed simulator consists of three major components - the power flow(PF) module, data conversion(COW) module and GU subsystem. PF module calculates power flow, and then checks overvoltage of buses and overflow of lines. COW module composes an Y-Bus array and a data base at each restoration action. The initial Y-Bus array is constructed from PSS/E data. The user friendly GUI subsystem is developed including graphic editor and built-in operation manual. As a result, the maximum processing time for one step operation is 15 seconds, which is adequate for training purpose. Comparison with PSS/E simulation proves the accuracy and reliability of the training system.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.21 no.5
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• pp.437-446
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• 2011

Performance of array sonars towed underwater is limited due to the self-noise induced mainly by the strumming vibration of the towing cable and also turbulent flow around the acoustic sensor module. The vibration of the towing cable generates axisymmetric waves that propagate along the acoustic module of the array sonar and produce self-noise. The present study aims to investigate the characteristics of the self-noise induced by the axisymmetric vibrations of the acoustic module. The waves of interest are the bulge and extensional waves propagating along the fluid-filled elastic hose. Dispersion relations of these waves are predicted by means of the numerical simulation to evaluate the wave speeds. The self-noise induced by the axisymmetric waves are formulated taking into account the damping of the elastic hose and the effect of the damping is investigated.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.5
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• pp.324-329
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• 2015

A decreased number of readout method is investigated to provide precise pixel information for small-animal positron emission tomography (PET). Small-animal PET consists of eight modules, and each module is composed of a $6{\times}6$ array of $2{\times}2{\times}20mm^3$ lutetium yttrium orthosilicate (LYSO) crystals optically coupled to a $4{\times}4$ array of $3{\times}3mm^2$ silicon photomultipliers (SiPMs). The number of readout channels is reduced by one-quarter that of the conventional method by applying a simplified row and column matrix algorithm. The performance of the PET system and detector module was evaluated with Geant4 Application for Emission Tomography (GATE) 6.1 and DETECT2000 simulations. In the results, all pixels of the $6{\times}6$ LYSO array were decoded well, and the spatial resolution and sensitivity, respectively, of the PET system were 1.75 mm and 4.6% (@ center of field of view, energy window: 350-650 keV).

• Nuclear Engineering and Technology
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• v.50 no.5
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• pp.780-787
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• 2018

This article presents a security module based on a field programmable gate array (FPGA) to mitigate man-in-the-middle cyber attacks. Nowadays, the FPGA is considered to be the state of the art in nuclear power plants I&C systems due to its flexibility, reconfigurability, and maintainability of the FPGA technology; it also provides acceptable solutions for embedded computing applications that require cybersecurity. The proposed FPGA-based security module is developed to mitigate information-gathering attacks, which can be made by gaining physical access to the network, e.g., a man-in-the-middle attack, using a cryptographic process to ensure data confidentiality and integrity and prevent injecting malware or malicious data into the critical digital assets of a nuclear power plant data communication system. A model-based system engineering approach is applied. System requirements analysis and enhanced function flow block diagrams are created and simulated using CORE9 to compare the performance of the current and developed systems. Hardware description language code for encryption and serial communication is developed using Vivado Design Suite 2017.2 as a programming tool to run the system synthesis and implementation for performance simulation and design verification. Simple windows are developed using Java for physical testing and communication between a personal computer and the FPGA.

• Proceedings of the KIEE Conference
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• 2004.11b
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• pp.204-207
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• 2004

The paper proposes a simulation model of grid-connected photovoltaic generation system (PV system) using on PSCAD/EMTDC, a reliable power system and apparatus transient analysis program. A equivalent circuit model of a solar cell is used for modeling solar array. A series of parameters required for array modeling are deduced from general specification data of a solar module. A PWM voltage source inverter (VSI) model is presented and current control scheme is implemented for VSI control. A maximum power point tracking (MPPT) technique is applied for controlling the PV system. Simulation case study provides V-I and V-P characteristics of solar array and PV system control performance for irradiation changes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.7
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• pp.1603-1609
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• 2010

This Paper deals with a design, making a prtotype and test methods of Real-time towed Line Array Sensor Data processing board for fast data communication and long range data transmission with SFM(Serial FPDP Module) through Optic-fiber channel. Towed line array sensors are installed in Frigate and the each LAS A, B, C group data from LAS is packed a previously agreed protocol and transmitted to the signal processing unit. Considering the limited space of VME 6U size, LAS Data processing board is designed with MPC8265 PowerPC Controller of Freescale for main system control and Altera's CycloneIII FPGA for sensor data packing, self-test simulation data generation, S/W FIFO et cetera. LAS Data processing board have VxWorks, the RTOS(Real Time Operating System) that present many device drivers, peripheral control libraries on board for real-time data processing.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.12
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• pp.2379-2384
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• 2009

In this paper, based on MATLAB which has characteristic that is simply applied to control algorithm and source modeling, photovoltaic modeling is implemented. Photovoltaic modeling is similarly performed PV array and simulated. Also, in order to output maximum power of PV, MPPT control is simulated. Moreover, simulation of converter is performed by means of PLECS (Piece wise Linear Electrical Simulation) which is easily made schematic of power electronics. Also, we compare simulation results and Sharp PV module and Suntech PV module. Finally, informative simulation of PV generation system is provided.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.9
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• pp.18-23
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• 2006

This paper presents an operator training simulator for power system restoration against massive blackout. The system is designed especially focused on the generality and convenient setting up for initial condition of simulation. The former is accomplished by using power flow calculation methodology, and PSS/E data is used to set up the initial state for easy setting. The proposed simulator consists of three major components-a power flow(PF), a data conversion(CONV), and, a GUI module. The PF module calculates power flow, and then checks over-voltages of buses and overloads of lines. The CONV module composes a Y-Bus array and a database at each restoration action. The initial Y-Bus array is composed from PSS/E data. A user friendly GUI module is developed including a graphic editor and a built-in operation manual. The maximum processing time for one step operation is 15 seconds, which is adequate for training purpose.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.3
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• pp.234-238
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• 2014

Multichip packaging was achieved the best solution to significantly reduce thermal resistance at the same time, to increase luminance intensity in LEDs packaging application. For the packaging, thermal spreading resistance is an important parameter to get influence the total thermal performance of LEDs. In this study, silicon-based multichip light emitting diodes (LEDs) packaged module has been examined for thermal characteristics in several parameters. Compared to the general conventional single LED packaged chip module, multichip LED packaged module has many advantages of low cost, low density, small size, and low thermal resistance. This analyzed module is comprised of multichip LED array, which consists of 32 LED packaged chips with supplement power of 0.2 W at every single chip. To realize the extent of thermal distribution, the computer-aided design model of 6.4 W Si-based multichip LED module was designed and was performed by the simulation basis of actual fabrication flow. The impact of thermal distribution is analyzed in alternative ways both optimizing numbers of fins and the thickness of that heatsink. In addition, a thermal resistance model was designed and derived from analytical theory. The optimum simulation results satisfies the expectations of the design goal and the measurement of IR camera results. tart after striking space key 2 times.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3199-3201
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• 1999

Convolutional coding with Viterbi decoding is known as a powerful method for forward error correction among many kinds of channel coding methods. This paper presents a soft decision Viterbi decoder which has systolic array trace-back architecture[1]. Soft decision is known as more effective method than hard decision and most of digital communication systems use soft decision. The advantage of using a systolic array decoder is that the trace-back operation can be accomplished continuously in an array of registers in a pipe-line fashion, instead of waiting for the entire trace-back procedure to be completed at each iteration. Therefore it may be suitable for faster communication system. We described operations of each module of the decoder and showed results of the logic synthesis and functional simulation.