• Journal of Korea Multimedia Society
• /
• v.3 no.4
• /
• pp.424-432
• /
• 2000

In this paper, we propose a new signaling method and circuits for interface between the host and LCD (Liquid Crystal Display) controller in the LCD system. The proposed circuits are allowed to transmit two data signals through modified-LVDS circuits and can reduce the operating frequency to a half. Then, we can solve EMI(Electro Magnetic Interference) problem and the power consumption by using differential signaling method. We have compared and analyzed the proposed method and the conventional methods in the power consumption and data rate. In addition, the proposed methods reduce hardware complexity significantly.

• Journal of Digital Convergence
• /
• v.10 no.11
• /
• pp.371-376
• /
• 2012

In this paper, we propose a new data coding method and its circuits for minimizing data transition in text image. The proposed circuits can solve the synchronization problem between input data and output data in the modified LVDS algorithm. And the proposed algorithm is allowed to transmit two data signals through additional serial data coding method in order to minimize the data transition in text image and can reduce the operating frequency to a half. Thus, we can solve EMI(Electro-Magnetic Interface) problem and reduce the power consumption. The simulation results show that the proposed algorithm and circuits can provide an enhanced data transition minimization in text image and solve the synchronization problem between input data and output data.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.62 no.2
• /
• pp.84-89
• /
• 2013

In this paper, we propose interface circuits for reducing power consumption and EMI when sequences of data from LCD controller to LCD driver IC by transmitting two bit data during one clock period. The proposed circuits are operated in current mode, which is different from conventional voltage-mode signaling techniques, and also employ threshold technique of Modified-LVDS(Low Voltage Differential Signaling) method. We have simulated the proposed circuits using H-SPICE tool for performance analysis of the proposed method. The simulation results show that the proposed circuits provide a faster transmission speed and stronger noise immunity than the conventional LVDS circuits. It might be suitable for the real-time transmission of huge image data in LCD system.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2009.10a
• /
• pp.1081-1085
• /
• 2009

We have already developed EMI reducing techniques using lossless compression by vertically differential EMI suppression method (VDE[1]). It applies lossless modulo reduction and data bit mapping optimization for low voltage differential signaling (LVDS) transmission lines, that reduces the probability of transient bit and EMI by 12 dB [6][7]. We also improved and optimized the VDE for low power LCD interface. With this modified VDE algorithm[8], the developed FPGA was measured the reduction of the power consumption of LCD circuit by more than 15 % compared to the conventional methods in the case of 14-in LCD with SXGA resolution. The VDE algorithm is based on the total image systematic approach. In the VDE method, the present image signals are subtracted for the 1H delayed image signals and transferred to a column driver through a PCB. As the vertical correlations for image signals are very high, we expected that most of the vertically subtracted image signals remain 0 level and transient cycles become very long. As a result, the power consumption and EMI are extremely reduced for the transferred image signals on a PCB. In this paper, we discussed our proposed method by emphasizing the fact that systematic approach are important based on not only display point of view but also total system point of view.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.2
• /
• pp.34-43
• /
• 2008

An OpenLDI receiver circuit for flat-panel display systems was designed and fabricated using $1.8-{\mu}m$ high-voltage CMOS technology. Designed circuit roughly consists of DLL circuit and parallelizers, which recovers clock and parallelize data bits, respectably. It has one clock input and four data inputs. Measurement results showed that it successfully recovers clock signal from input whose frequency is $10Mhz{\sim}65Mhz$, which corresponds data rate of $70Mbps{\sim}455Mbps$ per channel, or $280Mbps{\sim}1.82Gbps$ when all of the four data channels were utilized. A commercial LCD monitor was modified into a test-bench and used for video data transmission at clock frequency of 49Mhz. In the experiment, power consumption was 19mW for core block and 82.5mW for output buffer.